On Tue, 2025-05-13 at 16:42 +0300, Ville Syrjala wrote: > From: Ville Syrjälä <[email protected]> > > Hook up PIPEDMC interrupts. We'll need these for: > - flip queue signalling > - GTT/ATS faults on LNL+ > - random errors > > On LNL+ we get a new level of interrupts registers PIPEDMC_INTERRUPT*. > On earlier platforms we only have the INT_VECTOR field in the > PIPEDMC_STATUS registers, whose values are defined by the firmware. > > For now we'll enable the interrupts on LNL+ only. For earlier platforms > it's not clear that there is any use for these interrupts, and some > ADL machines have exhibited spurious DE_PIPE interrupts with the > PIPEDMC interrupts unmasked/enabled. We can revisit enabling these > for earlier platforms in the future. > > Similar to DSB interrupt registers, the unused bits in > PIPEDMC_INTERRUPT* seem to act like randomg r/w bits (instead > of being hardwired to 0 like one would expect), and so we'll try > to avoid setting them so that we don't mistake them for real > interrupts. > > v2: Only enable/unmask for LNL+ > Keep the flip queue interrupt masked off for now since > we don't have a use for it yet > > Reviewed-by: Luca Coelho <[email protected]> #v1 > Signed-off-by: Ville Syrjälä <[email protected]> > ---
Renewing my r-b. Reviewed-by: Luca Coelho <[email protected]> -- Cheers, Luca.
