On 4/28/2025 11:50 AM, Mitul Golani wrote:
Add state checker for dc balance params. Also add macro to
check source support.
This is now introducing the new member for tracking vrr dc balancing,
the commit message and the subject should reflect the same.
--v3: Seggregate crtc_state params with this patch. (Ankit)
Signed-off-by: Mitul Golani <[email protected]>
---
drivers/gpu/drm/i915/display/intel_display.c | 8 +++++++
.../drm/i915/display/intel_display_types.h | 7 +++++++
drivers/gpu/drm/i915/display/intel_vrr.c | 21 +++++++++++++++++++
3 files changed, 36 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index 58845b74f17d..1cd9c65da576 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -5403,6 +5403,14 @@ intel_pipe_config_compare(const struct intel_crtc_state
*current_config,
PIPE_CONF_CHECK_LLI(cmrr.cmrr_m);
PIPE_CONF_CHECK_LLI(cmrr.cmrr_n);
PIPE_CONF_CHECK_BOOL(cmrr.enable);
+ PIPE_CONF_CHECK_BOOL(vrr.dc_balance.enable);
+ PIPE_CONF_CHECK_I(vrr.dc_balance.vmin);
+ PIPE_CONF_CHECK_I(vrr.dc_balance.vmax);
+ PIPE_CONF_CHECK_I(vrr.dc_balance.guardband);
+ PIPE_CONF_CHECK_I(vrr.dc_balance.slope);
+ PIPE_CONF_CHECK_I(vrr.dc_balance.max_increase);
+ PIPE_CONF_CHECK_I(vrr.dc_balance.max_decrease);
+ PIPE_CONF_CHECK_I(vrr.dc_balance.vblank_target);
}
if (!fastset || intel_vrr_always_use_vrr_tg(display)) {
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
b/drivers/gpu/drm/i915/display/intel_display_types.h
index 7415564d058a..e6b5bec748cd 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1308,6 +1308,13 @@ struct intel_crtc_state {
u8 pipeline_full;
u16 flipline, vmin, vmax, guardband;
u32 vsync_end, vsync_start;
+ struct {
+ bool enable;
+ u16 vmin, vmax;
+ u16 guardband, slope;
+ u16 max_increase, max_decrease;
+ u16 vblank_target;
+ } dc_balance;
} vrr;
/* Content Match Refresh Rate state */
diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c
b/drivers/gpu/drm/i915/display/intel_vrr.c
index ab4f8def821c..55923eadc3c1 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -10,6 +10,7 @@
#include "intel_de.h"
#include "intel_display_types.h"
#include "intel_dp.h"
+#include "intel_dmc_regs.h"
#include "intel_vrr.h"
#include "intel_vrr_regs.h"
@@ -738,6 +739,26 @@ void intel_vrr_get_config(struct intel_crtc_state *crtc_state)
else
crtc_state->vrr.enable = vrr_enable;
+ if (HAS_VRR_DC_BALANCE(display)) {
+ crtc_state->vrr.dc_balance.enable =
+ intel_de_read(display, PIPEDMC_DCB_CTL(display,
cpu_transcoder)) &
+ PIPEDMC_ADAPTIVE_DCB_ENABLE;
+ crtc_state->vrr.dc_balance.vmin =
+ intel_de_read(display, PIPEDMC_DCB_VMIN(display,
cpu_transcoder)) + 1;
+ crtc_state->vrr.dc_balance.vmax =
+ intel_de_read(display, PIPEDMC_DCB_VMAX(display,
cpu_transcoder)) + 1;
+ crtc_state->vrr.dc_balance.guardband =
IMHO, 1 should be added only if the value read is > 0. Otherwise it will
give mismatches for cases where vrr is not enabled.
Regards,
Ankit
+ intel_de_read(display, PIPEDMC_DCB_GUARDBAND(display,
cpu_transcoder));
+ crtc_state->vrr.dc_balance.max_increase =
+ intel_de_read(display,
PIPEDMC_DCB_MAX_INCREASE(display, cpu_transcoder));
+ crtc_state->vrr.dc_balance.max_decrease =
+ intel_de_read(display,
PIPEDMC_DCB_MAX_DECREASE(display, cpu_transcoder));
+ crtc_state->vrr.dc_balance.slope =
+ intel_de_read(display, PIPEDMC_DCB_SLOPE(display,
cpu_transcoder));
+ crtc_state->vrr.dc_balance.vblank_target =
+ intel_de_read(display, PIPEDMC_DCB_VBLANK(display,
cpu_transcoder));
+ }
+
/*
* #TODO: For Both VRR and CMRR the flag I915_MODE_FLAG_VRR is set for
mode_flags.
* Since CMRR is currently disabled, set this flag for VRR for now.
