On 4/28/2025 11:50 AM, Mitul Golani wrote:
Add registers and access bits for DC Balance enable.
Signed-off-by: Mitul Golani <[email protected]>
---
drivers/gpu/drm/i915/display/intel_dmc_regs.h | 55 +++++++++++++++++++
drivers/gpu/drm/i915/display/intel_vrr_regs.h | 50 +++++++++++++++++
2 files changed, 105 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_dmc_regs.h
b/drivers/gpu/drm/i915/display/intel_dmc_regs.h
index e16ea3f16ed8..a376499fbfab 100644
--- a/drivers/gpu/drm/i915/display/intel_dmc_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_dmc_regs.h
@@ -117,4 +117,59 @@
#define DMC_WAKELOCK_CTL_REQ REG_BIT(31)
#define DMC_WAKELOCK_CTL_ACK REG_BIT(15)
+#define _PIPEDMC_DCB_CTL_A 0x5F1A0
+#define _PIPEDMC_DCB_CTL_B 0x5F5A0
+#define _PIPEDMC_DCB_CTL_C 0x5F9A0
+#define _PIPEDMC_DCB_CTL_D 0x5FDA0
+#define PIPEDMC_DCB_CTL(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans,
_PIPEDMC_DCB_CTL_A)
Use MMIO_PIPE here.
Perhaps only A and B offsets are sufficient. Though in many places we
have all offsets, IMHO only 2 should be sufficient if the offsets have
constant difference for each pipe.
Also, it would be better to have separate patch for VRR registers
required for DC balancing adjustments.
Regards,
Ankit
+#define PIPEDMC_ADAPTIVE_DCB_ENABLE REG_BIT(31)
+
+#define _PIPEDMC_DCB_VBLANK_A 0x5F1BC
+#define _PIPEDMC_DCB_VBLANK_B 0x5F5BC
+#define _PIPEDMC_DCB_VBLANK_C 0x5F9BC
+#define _PIPEDMC_DCB_VBLANK_D 0x5FDBC
+#define PIPEDMC_DCB_VBLANK(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans,
_PIPEDMC_DCB_VBLANK_A)
+
+#define _PIPEDMC_DCB_SLOPE_A 0x5F1B8
+#define _PIPEDMC_DCB_SLOPE_B 0x5F5B8
+#define _PIPEDMC_DCB_SLOPE_C 0x5F9B8
+#define _PIPEDMC_DCB_SLOPE_D 0x5FDB8
+#define PIPEDMC_DCB_SLOPE(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans,
_PIPEDMC_DCB_SLOPE_A)
+
+#define _PIPEDMC_DCB_GUARDBAND_A 0x5F1B4
+#define _PIPEDMC_DCB_GUARDBAND_B 0x5F5B4
+#define _PIPEDMC_DCB_GUARDBAND_C 0x5F9B4
+#define _PIPEDMC_DCB_GUARDBAND_D 0x5FDB4
+#define PIPEDMC_DCB_GUARDBAND(dev_priv, trans) _MMIO_TRANS2(dev_priv, \
+ trans, \
+
_PIPEDMC_DCB_GUARDBAND_A)
+
+#define _PIPEDMC_DCB_MAX_INCREASE_A 0x5F1AC
+#define _PIPEDMC_DCB_MAX_INCREASE_B 0x5F5AC
+#define _PIPEDMC_DCB_MAX_INCREASE_C 0x5F9AC
+#define _PIPEDMC_DCB_MAX_INCREASE_D 0x5FDAC
+#define PIPEDMC_DCB_MAX_INCREASE(dev_priv, trans) _MMIO_TRANS2(dev_priv, \
+ trans, \
+
_PIPEDMC_DCB_MAX_INCREASE_A)
+
+#define _PIPEDMC_DCB_MAX_DECREASE_A 0x5F1B0
+#define _PIPEDMC_DCB_MAX_DECREASE_B 0x5F5B0
+#define _PIPEDMC_DCB_MAX_DECREASE_C 0x5F9B0
+#define _PIPEDMC_DCB_MAX_DECREASE_D 0x5FDB0
+#define PIPEDMC_DCB_MAX_DECREASE(dev_priv, trans) _MMIO_TRANS2(dev_priv, \
+ trans, \
+
_PIPEDMC_DCB_MAX_DECREASE_A)
+
+#define _PIPEDMC_DCB_VMIN_A 0x5F1A4
+#define _PIPEDMC_DCB_VMIN_B 0x5F5A4
+#define _PIPEDMC_DCB_VMIN_C 0x5F9A4
+#define _PIPEDMC_DCB_VMIN_D 0x5FDA4
+#define PIPEDMC_DCB_VMIN(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans,
_PIPEDMC_DCB_VMIN_A)
+
+#define _PIPEDMC_DCB_VMAX_A 0x5F1A8
+#define _PIPEDMC_DCB_VMAX_B 0x5F5A8
+#define _PIPEDMC_DCB_VMAX_C 0x5F9A8
+#define _PIPEDMC_DCB_VMAX_D 0x5FDA8
+#define PIPEDMC_DCB_VMAX(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans,
_PIPEDMC_DCB_VMAX_A)
+
#endif /* __INTEL_DMC_REGS_H__ */
diff --git a/drivers/gpu/drm/i915/display/intel_vrr_regs.h
b/drivers/gpu/drm/i915/display/intel_vrr_regs.h
index 6ed0e0dc97e7..1fdba51b4bbd 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_vrr_regs.h
@@ -9,6 +9,56 @@
#include "intel_display_reg_defs.h"
/* VRR registers */
+#define _TRANS_VRR_DCB_ADJ_FLIPLINE_CFG_A 0x604D4
+#define _TRANS_VRR_DCB_ADJ_FLIPLINE_CFG_B 0x614D4
+#define _TRANS_VRR_DCB_ADJ_FLIPLINE_CFG_C 0x624D4
+#define _TRANS_VRR_DCB_ADJ_FLIPLINE_CFG_D 0x634D4
+#define TRANS_VRR_DCB_ADJ_FLIPLINE_CFG(dev_priv, trans) \
+ _MMIO_TRANS2(dev_priv, \
+ trans, \
+
_TRANS_VRR_DCB_ADJ_FLIPLINE_CFG_A)
+
+#define _TRANS_VRR_DCB_ADJ_VMAX_CFG_A 0x604D8
+#define _TRANS_VRR_DCB_ADJ_VMAX_CFG_B 0x614D8
+#define _TRANS_VRR_DCB_ADJ_VMAX_CFG_C 0x624D8
+#define _TRANS_VRR_DCB_ADJ_VMAX_CFG_D 0x634D8
+#define TRANS_VRR_DCB_ADJ_VMAX_CFG(dev_priv, trans) _MMIO_TRANS2(dev_priv, \
+ trans, \
+
_TRANS_VRR_DCB_ADJ_VMAX_CFG_A)
+
+#define _TRANS_VRR_FLIPLINE_DCB_A 0x60418
+#define _TRANS_VRR_FLIPLINE_DCB_B 0x61418
+#define _TRANS_VRR_FLIPLINE_DCB_C 0x62418
+#define _TRANS_VRR_FLIPLINE_DCB_D 0x63418
+#define TRANS_VRR_FLIPLINE_DCB(dev_priv, trans) _MMIO_TRANS2(dev_priv, \
+ trans, \
+
_TRANS_VRR_FLIPLINE_DCB_A)
+
+#define _TRANS_VRR_VMAX_DCB_A 0x60414
+#define _TRANS_VRR_VMAX_DCB_B 0x61414
+#define _TRANS_VRR_VMAX_DCB_C 0x62414
+#define _TRANS_VRR_VMAX_DCB_D 0x63414
+#define TRANS_VRR_VMAX_DCB(dev_priv, trans) _MMIO_TRANS2(dev_priv, \
+ trans, \
+
_TRANS_VRR_VMAX_DCB_A)
+
+#define VRR_DCB_ADJ_FLIPLINE_CNT_MASK REG_GENMASK(31, 24)
+#define VRR_DCB_ADJ_FLIPLINE_MASK REG_GENMASK(19, 0)
+#define VRR_DCB_ADJ_VMAX_CNT_MASK REG_GENMASK(31, 24)
+#define VRR_DCB_ADJ_VMAX_MASK REG_GENMASK(19, 0)
+#define VRR_FLIPLINE_DCB_MASK REG_GENMASK(19, 0)
+#define VRR_VMAX_DCB_MASK REG_GENMASK(19, 0)
+#define VRR_CTL_DCB_ADJ_ENABLE REG_BIT(28)
+
+#define _TRANS_ADAPTIVE_SYNC_DCB_CTL_A 0x604C0
+#define _TRANS_ADAPTIVE_SYNC_DCB_CTL_B 0x614C0
+#define _TRANS_ADAPTIVE_SYNC_DCB_CTL_C 0x624C0
+#define _TRANS_ADAPTIVE_SYNC_DCB_CTL_D 0x634C0
+#define TRANS_ADAPTIVE_SYNC_DCB_CTL(dev_priv, trans) _MMIO_TRANS2(dev_priv, \
+ trans, \
+
_TRANS_ADAPTIVE_SYNC_DCB_CTL_A)
+#define ADAPTIVE_SYNC_COUNTER_EN REG_BIT(31)
+
#define _TRANS_VRR_CTL_A 0x60420
#define _TRANS_VRR_CTL_B 0x61420
#define _TRANS_VRR_CTL_C 0x62420
