On Fri, 04 Apr 2025, Arun R Murthy <[email protected]> wrote: > Remove the pll state table for UHBR13.5 on synps and c20 PHY as UHBR13.5 > is removed in previous patch.
Subject should be about the PHY, not about DP. drm/i915/display/dp is excessive anyway. There's no "previous patch" once this is committed. Don't mention patches in commit messages. And it might not be "previous" anyway. synps is a typo. > > Signed-off-by: Arun R Murthy <[email protected]> > --- > drivers/gpu/drm/i915/display/intel_cx0_phy.c | 26 -------------------- > drivers/gpu/drm/i915/display/intel_snps_phy.c | 35 > --------------------------- > 2 files changed, 61 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c > b/drivers/gpu/drm/i915/display/intel_cx0_phy.c > index > 22595766eac5332e541f3441bed80a187dc80224..398e207159876a54472560087b5841ca372b4c01 > 100644 > --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c > +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c > @@ -902,31 +902,6 @@ static const struct intel_c20pll_state mtl_c20_dp_uhbr10 > = { > }, > }; > > -static const struct intel_c20pll_state mtl_c20_dp_uhbr13_5 = { > - .clock = 1350000, /* 13.5 Gbps */ > - .tx = { 0xbea0, /* tx cfg0 */ > - 0x4800, /* tx cfg1 */ > - 0x0000, /* tx cfg2 */ > - }, > - .cmn = {0x0500, /* cmn cfg0*/ > - 0x0005, /* cmn cfg1 */ > - 0x0000, /* cmn cfg2 */ > - 0x0000, /* cmn cfg3 */ > - }, > - .mpllb = { 0x015f, /* mpllb cfg0 */ > - 0x2205, /* mpllb cfg1 */ > - 0x1b17, /* mpllb cfg2 */ > - 0xffc1, /* mpllb cfg3 */ > - 0xe100, /* mpllb cfg4 */ > - 0xbd00, /* mpllb cfg5 */ > - 0x2000, /* mpllb cfg6 */ > - 0x0001, /* mpllb cfg7 */ > - 0x4800, /* mpllb cfg8 */ > - 0x0000, /* mpllb cfg9 */ > - 0x0000, /* mpllb cfg10 */ > - }, > -}; > - > static const struct intel_c20pll_state mtl_c20_dp_uhbr20 = { > .clock = 2000000, /* 20 Gbps */ > .tx = { 0xbe20, /* tx cfg0 */ > @@ -957,7 +932,6 @@ static const struct intel_c20pll_state * const > mtl_c20_dp_tables[] = { > &mtl_c20_dp_hbr2, > &mtl_c20_dp_hbr3, > &mtl_c20_dp_uhbr10, > - &mtl_c20_dp_uhbr13_5, > &mtl_c20_dp_uhbr20, > NULL, > }; > diff --git a/drivers/gpu/drm/i915/display/intel_snps_phy.c > b/drivers/gpu/drm/i915/display/intel_snps_phy.c > index > b9acd9fe160cde7de682b48648eb183a0549b014..79a6d14d7592a35ba51c52f6fe26564f3e1c1340 > 100644 > --- a/drivers/gpu/drm/i915/display/intel_snps_phy.c > +++ b/drivers/gpu/drm/i915/display/intel_snps_phy.c > @@ -215,47 +215,12 @@ static const struct intel_mpllb_state dg2_dp_uhbr10_100 > = { > REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_STEPSIZE, 76101), > }; > > -static const struct intel_mpllb_state dg2_dp_uhbr13_100 = { > - .clock = 1350000, > - .ref_control = > - REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3), > - .mpllb_cp = > - REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 5) | > - REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 45) | > - REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 65) | > - REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 127), > - .mpllb_div = > - REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) | > - REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV_CLK_EN, 1) | > - REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV_MULTIPLIER, 8) | > - REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) | > - REG_FIELD_PREP(SNPS_PHY_MPLLB_WORD_DIV2_EN, 1) | > - REG_FIELD_PREP(SNPS_PHY_MPLLB_DP2_MODE, 1) | > - REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 3), > - .mpllb_div2 = > - REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 2) | > - REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 508), > - .mpllb_fracn1 = > - REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) | > - REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 1), > - > - /* > - * SSC will be enabled, DP UHBR has a minimum SSC requirement. > - */ > - .mpllb_sscen = > - REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_EN, 1) | > - REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_PEAK, 79626), > - .mpllb_sscstep = > - REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_STEPSIZE, 102737), > -}; > - > static const struct intel_mpllb_state * const dg2_dp_100_tables[] = { > &dg2_dp_rbr_100, > &dg2_dp_hbr1_100, > &dg2_dp_hbr2_100, > &dg2_dp_hbr3_100, > &dg2_dp_uhbr10_100, > - &dg2_dp_uhbr13_100, > NULL, > }; -- Jani Nikula, Intel
