While enabling pipe currently we use the non vrr timings first and then enable the VRR timings later. >From XE2LPD+ we will always have VRR timing generarator in use, so start the transcoder in vrr mode.
Signed-off-by: Ankit Nautiyal <[email protected]> --- drivers/gpu/drm/i915/display/intel_display.c | 12 ++++++++++-- drivers/gpu/drm/i915/display/intel_vblank.c | 8 +++++--- 2 files changed, 15 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index a62353948686..6d12a9b620be 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -7142,8 +7142,16 @@ static void intel_enable_crtc(struct intel_atomic_state *state, const struct intel_crtc_state *pipe_crtc_state = intel_atomic_get_new_crtc_state(state, pipe_crtc); - /* VRR will be enable later, if required */ - intel_crtc_update_active_timings(pipe_crtc_state, false); + /* + * For XE2LPD+ we are always using VRR TG. + * For previous platforms VRR will be enable later, if required + */ + if (DISPLAY_VER(dev_priv) >= 20) + intel_crtc_update_active_timings(pipe_crtc_state, + pipe_crtc_state->vrr.tg_enable); + else + intel_crtc_update_active_timings(pipe_crtc_state, false); + } dev_priv->display.funcs.display->crtc_enable(state, crtc); diff --git a/drivers/gpu/drm/i915/display/intel_vblank.c b/drivers/gpu/drm/i915/display/intel_vblank.c index a95fb3349eba..ca4a6add6926 100644 --- a/drivers/gpu/drm/i915/display/intel_vblank.c +++ b/drivers/gpu/drm/i915/display/intel_vblank.c @@ -626,9 +626,11 @@ void intel_vblank_evade_init(const struct intel_crtc_state *old_crtc_state, adjusted_mode = &crtc_state->hw.adjusted_mode; if (crtc->mode_flags & I915_MODE_FLAG_VRR) { - /* timing changes should happen with VRR disabled */ - drm_WARN_ON(crtc->base.dev, intel_crtc_needs_modeset(new_crtc_state) || - new_crtc_state->update_m_n || new_crtc_state->update_lrr); + /* Prior to XE2LPD+, timing changes should happen with VRR disabled */ + if (DISPLAY_VER(display) < 20) { + drm_WARN_ON(crtc->base.dev, intel_crtc_needs_modeset(new_crtc_state) || + new_crtc_state->update_m_n || new_crtc_state->update_lrr); + } if (intel_vrr_is_push_sent(crtc_state)) evade->vblank_start = intel_vrr_vmin_vblank_start(crtc_state); -- 2.45.2
