Cleanup register definitions for DSS CLT reg bits. Replace the hand rolled (1<<n) with the modern REG_BIT(). Use REG_GENMASK and REG_FIELD_PREP for the bit fields.
Signed-off-by: Ankit Nautiyal <[email protected]> --- drivers/gpu/drm/i915/display/intel_dss_regs.h | 34 ++++++++++--------- 1 file changed, 18 insertions(+), 16 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dss_regs.h b/drivers/gpu/drm/i915/display/intel_dss_regs.h index b1e24ea027c3..cfc8ef451917 100644 --- a/drivers/gpu/drm/i915/display/intel_dss_regs.h +++ b/drivers/gpu/drm/i915/display/intel_dss_regs.h @@ -10,35 +10,37 @@ /* Display Stream Splitter Control */ #define DSS_CTL1 _MMIO(0x67400) -#define SPLITTER_ENABLE (1 << 31) -#define JOINER_ENABLE (1 << 30) -#define DUAL_LINK_MODE_INTERLEAVE (1 << 24) +#define SPLITTER_ENABLE REG_BIT(31) +#define JOINER_ENABLE REG_BIT(30) +#define DUAL_LINK_MODE_INTERLEAVE REG_BIT(24) #define DUAL_LINK_MODE_FRONTBACK (0 << 24) -#define OVERLAP_PIXELS_MASK (0xf << 16) -#define OVERLAP_PIXELS(pixels) ((pixels) << 16) -#define LEFT_DL_BUF_TARGET_DEPTH_MASK (0xfff << 0) -#define LEFT_DL_BUF_TARGET_DEPTH(pixels) ((pixels) << 0) +#define OVERLAP_PIXELS_MASK REG_GENMASK(19, 16) +#define OVERLAP_PIXELS(pixels) REG_FIELD_PREP(OVERLAP_PIXELS_MASK, pixels) +#define LEFT_DL_BUF_TARGET_DEPTH_MASK REG_GENMASK(11, 0) +#define LEFT_DL_BUF_TARGET_DEPTH(pixels) REG_FIELD_PREP(LEFT_DL_BUF_TARGET_DEPTH_MASK, \ + pixels) #define MAX_DL_BUFFER_TARGET_DEPTH 0x5a0 #define DSS_CTL2 _MMIO(0x67404) -#define LEFT_BRANCH_VDSC_ENABLE (1 << 31) -#define RIGHT_BRANCH_VDSC_ENABLE (1 << 15) -#define RIGHT_DL_BUF_TARGET_DEPTH_MASK (0xfff << 0) -#define RIGHT_DL_BUF_TARGET_DEPTH(pixels) ((pixels) << 0) +#define LEFT_BRANCH_VDSC_ENABLE REG_BIT(31) +#define RIGHT_BRANCH_VDSC_ENABLE REG_BIT(15) +#define RIGHT_DL_BUF_TARGET_DEPTH_MASK REG_GENMASK(11, 0) +#define RIGHT_DL_BUF_TARGET_DEPTH(pixels) REG_FIELD_PREP(RIGHT_DL_BUF_TARGET_DEPTH_MASK,\ + pixels) #define _ICL_PIPE_DSS_CTL1_PB 0x78200 #define _ICL_PIPE_DSS_CTL1_PC 0x78400 #define ICL_PIPE_DSS_CTL1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ _ICL_PIPE_DSS_CTL1_PB, \ _ICL_PIPE_DSS_CTL1_PC) -#define BIG_JOINER_ENABLE (1 << 29) -#define PRIMARY_BIG_JOINER_ENABLE (1 << 28) -#define VGA_CENTERING_ENABLE (1 << 27) +#define BIG_JOINER_ENABLE REG_BIT(29) +#define PRIMARY_BIG_JOINER_ENABLE REG_BIT(28) +#define VGA_CENTERING_ENABLE REG_BIT(27) #define SPLITTER_CONFIGURATION_MASK REG_GENMASK(26, 25) #define SPLITTER_CONFIGURATION_2_SEGMENT REG_FIELD_PREP(SPLITTER_CONFIGURATION_MASK, 0) #define SPLITTER_CONFIGURATION_4_SEGMENT REG_FIELD_PREP(SPLITTER_CONFIGURATION_MASK, 1) -#define UNCOMPRESSED_JOINER_PRIMARY (1 << 21) -#define UNCOMPRESSED_JOINER_SECONDARY (1 << 20) +#define UNCOMPRESSED_JOINER_PRIMARY REG_BIT(21) +#define UNCOMPRESSED_JOINER_SECONDARY REG_BIT(20) #define _ICL_PIPE_DSS_CTL2_PB 0x78204 #define _ICL_PIPE_DSS_CTL2_PC 0x78404 -- 2.45.2
