On Wed, 18 Oct 2023, Ville Syrjala <[email protected]> wrote: > From: Ville Syrjälä <[email protected]> > > Follow the bspec sequqnece more closely and clear ACT sent just ^ sequence
> before triggering the allocation. Can't see why we'd want to > deviate from the spec sequence here. > > Signed-off-by: Ville Syrjälä <[email protected]> > --- > drivers/gpu/drm/i915/display/intel_dp_mst.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c > b/drivers/gpu/drm/i915/display/intel_dp_mst.c > index 57eb581b8a50..3c66a3e3cc5e 100644 > --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c > +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c > @@ -791,8 +791,6 @@ static void intel_mst_enable_dp(struct intel_atomic_state > *state, > > drm_WARN_ON(&dev_priv->drm, pipe_config->has_pch_encoder); > > - clear_act_sent(encoder, pipe_config); > - > if (intel_dp_is_uhbr(pipe_config)) { > const struct drm_display_mode *adjusted_mode = > &pipe_config->hw.adjusted_mode; > @@ -806,6 +804,8 @@ static void intel_mst_enable_dp(struct intel_atomic_state > *state, > > intel_ddi_enable_transcoder_func(encoder, pipe_config); > > + clear_act_sent(encoder, pipe_config); > + > intel_de_rmw(dev_priv, TRANS_DDI_FUNC_CTL(trans), 0, > TRANS_DDI_DP_VC_PAYLOAD_ALLOC); -- Jani Nikula, Intel
