On Wed, 18 Oct 2023, Ville Syrjala <[email protected]> wrote: > From: Ville Syrjälä <[email protected]> > > The DP modeset sequence asks us to disable TRANSCONF before clearing > the FECSTALL_DIS_DPTSTREAM_DPTTG bit, although we are still asked > to wait for the transcoder to stop only after both steps have > been done. > > Signed-off-by: Ville Syrjälä <[email protected]>
Reviewed-by: Jani Nikula <[email protected]> > --- > drivers/gpu/drm/i915/display/intel_display.c | 3 ++- > 1 file changed, 2 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_display.c > b/drivers/gpu/drm/i915/display/intel_display.c > index 28d85e1e858e..a994fc2319a3 100644 > --- a/drivers/gpu/drm/i915/display/intel_display.c > +++ b/drivers/gpu/drm/i915/display/intel_display.c > @@ -485,6 +485,8 @@ void intel_disable_transcoder(const struct > intel_crtc_state *old_crtc_state) > if (!IS_I830(dev_priv)) > val &= ~TRANSCONF_ENABLE; > > + intel_de_write(dev_priv, reg, val); > + > if (DISPLAY_VER(dev_priv) >= 14) > intel_de_rmw(dev_priv, MTL_CHICKEN_TRANS(cpu_transcoder), > FECSTALL_DIS_DPTSTREAM_DPTTG, 0); > @@ -492,7 +494,6 @@ void intel_disable_transcoder(const struct > intel_crtc_state *old_crtc_state) > intel_de_rmw(dev_priv, CHICKEN_TRANS(cpu_transcoder), > FECSTALL_DIS_DPTSTREAM_DPTTG, 0); > > - intel_de_write(dev_priv, reg, val); > if ((val & TRANSCONF_ENABLE) == 0) > intel_wait_for_pipe_off(old_crtc_state); > } -- Jani Nikula, Intel
