From: Ville Syrjälä <[email protected]> ILK should work pretty much the same as SNB, except it doesn't have the blitter, so we only care about render tracking.
Signed-off-by: Ville Syrjälä <[email protected]> --- drivers/gpu/drm/i915/i915_reg.h | 2 +- drivers/gpu/drm/i915/intel_pm.c | 2 -- drivers/gpu/drm/i915/intel_ringbuffer.c | 57 +++++++++++++++++---------------- 3 files changed, 31 insertions(+), 30 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 1777beb..db532cf 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -1091,7 +1091,7 @@ #define ILK_DPFC_CHICKEN 0x43224 #define ILK_FBC_RT_BASE 0x2128 #define ILK_FBC_RT_VALID (1<<0) -#define SNB_FBC_FRONT_BUFFER (1<<1) +#define ILK_FBC_FRONT_BUFFER (1<<1) #define ILK_DISPLAY_CHICKEN1 0x42000 #define ILK_FBCQ_DIS (1<<22) diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index f46bb56..4039aa3 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -210,8 +210,6 @@ static void ironlake_enable_fbc(struct drm_crtc *crtc, (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) | (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT)); I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y); - if (IS_GEN5(dev)) - I915_WRITE(ILK_FBC_RT_BASE, i915_gem_obj_ggtt_offset(obj) | ILK_FBC_RT_VALID); /* enable it... */ I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN); diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c index 2e62d76..a02d472 100644 --- a/drivers/gpu/drm/i915/intel_ringbuffer.c +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c @@ -77,6 +77,32 @@ gen2_render_ring_flush(struct intel_ring_buffer *ring, return 0; } +static int gen5_render_fbc_tracking(struct intel_ring_buffer *ring) +{ + int ret; + + if (!ring->fbc_address_dirty) + return 0; + + ret = intel_ring_begin(ring, 4); + if (ret) + return ret; + + intel_ring_emit(ring, MI_NOOP); + intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); + intel_ring_emit(ring, ILK_FBC_RT_BASE); + if (ring->fbc_address != -1) + intel_ring_emit(ring, ring->fbc_address | + ILK_FBC_FRONT_BUFFER | ILK_FBC_RT_VALID); + else + intel_ring_emit(ring, 0); + intel_ring_advance(ring); + + ring->fbc_address_dirty = false; + + return 0; +} + static int gen4_render_ring_flush(struct intel_ring_buffer *ring, u32 invalidate_domains, @@ -132,6 +158,9 @@ gen4_render_ring_flush(struct intel_ring_buffer *ring, intel_ring_emit(ring, MI_NOOP); intel_ring_advance(ring); + if (invalidate_domains && IS_GEN5(dev)) + return gen5_render_fbc_tracking(ring); + return 0; } @@ -232,32 +261,6 @@ static int gen6_blt_fbc_tracking(struct intel_ring_buffer *ring) return 0; } -static int gen6_render_fbc_tracking(struct intel_ring_buffer *ring) -{ - int ret; - - if (!ring->fbc_address_dirty) - return 0; - - ret = intel_ring_begin(ring, 4); - if (ret) - return ret; - - intel_ring_emit(ring, MI_NOOP); - intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); - intel_ring_emit(ring, ILK_FBC_RT_BASE); - if (ring->fbc_address != -1) - intel_ring_emit(ring, ring->fbc_address | - SNB_FBC_FRONT_BUFFER | ILK_FBC_RT_VALID); - else - intel_ring_emit(ring, 0); - intel_ring_advance(ring); - - ring->fbc_address_dirty = false; - - return 0; -} - static int gen6_render_ring_flush(struct intel_ring_buffer *ring, u32 invalidate_domains, u32 flush_domains) @@ -308,7 +311,7 @@ gen6_render_ring_flush(struct intel_ring_buffer *ring, intel_ring_advance(ring); if (invalidate_domains) - return gen6_render_fbc_tracking(ring); + return gen5_render_fbc_tracking(ring); return 0; } -- 1.8.3.2 _______________________________________________ Intel-gfx mailing list [email protected] http://lists.freedesktop.org/mailman/listinfo/intel-gfx
