The bspec was recently updated with new cdclk values 324mhz and 326.4mhz. These clock values are the first ones on gen11+ that use a CD2X clock divider of /2 rather than /1 so we need a little bit of extra logic to program the divider properly before actually enabling them.
Note that the bspec does have a note next to the /1 divider bits saying "Use this setting for all CD frequencies" on gen11. I suspect that this note is left over from before these new frequencies were added, but I'm still confirming that with the hardware team. The note does not appear on the TGL bspec. Cc: José Roberto de Souza <[email protected]> Cc: Lucas De Marchi <[email protected]> Matt Roper (2): drm/i915: Allow /2 CD2X divider on gen11+ drm/i915: Add 324mhz and 326.4mhz cdclks for gen11+ drivers/gpu/drm/i915/display/intel_cdclk.c | 98 +++++++++------------- drivers/gpu/drm/i915/i915_reg.h | 1 + 2 files changed, 42 insertions(+), 57 deletions(-) -- 2.20.1 _______________________________________________ Intel-gfx mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/intel-gfx
