On Wed, Dec 12, 2018 at 11:17:38PM +0200, Ville Syrjala wrote: > From: Ville Syrjälä <[email protected]> > > Remove the hand rolled array of WM0_PIPE register offsets > and use the standard _MMIO_PIPE3() instead. > > v2: Take care of gvt too > > Signed-off-by: Ville Syrjälä <[email protected]>
Reviewed-by: Lucas De Marchi <[email protected]> Lucas De Marchi > --- > drivers/gpu/drm/i915/gvt/handlers.c | 6 +++--- > drivers/gpu/drm/i915/i915_reg.h | 9 +++++---- > drivers/gpu/drm/i915/intel_pm.c | 13 ++++--------- > 3 files changed, 12 insertions(+), 16 deletions(-) > > diff --git a/drivers/gpu/drm/i915/gvt/handlers.c > b/drivers/gpu/drm/i915/gvt/handlers.c > index b5475c91e2ef..2edab387221d 100644 > --- a/drivers/gpu/drm/i915/gvt/handlers.c > +++ b/drivers/gpu/drm/i915/gvt/handlers.c > @@ -2120,9 +2120,9 @@ static int init_generic_mmio_info(struct intel_gvt *gvt) > MMIO_D(PF_VSCALE(PIPE_C), D_ALL); > MMIO_D(PF_HSCALE(PIPE_C), D_ALL); > > - MMIO_D(WM0_PIPEA_ILK, D_ALL); > - MMIO_D(WM0_PIPEB_ILK, D_ALL); > - MMIO_D(WM0_PIPEC_IVB, D_ALL); > + MMIO_D(WM0_PIPE_ILK(PIPE_A), D_ALL); > + MMIO_D(WM0_PIPE_ILK(PIPE_B), D_ALL); > + MMIO_D(WM0_PIPE_ILK(PIPE_C), D_ALL); > MMIO_D(WM1_LP_ILK, D_ALL); > MMIO_D(WM2_LP_ILK, D_ALL); > MMIO_D(WM3_LP_ILK, D_ALL); > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index ea9a664980a6..246e5e77e7c5 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -5992,15 +5992,16 @@ enum { > _MMIO(_PLANE(plane, _PLANE_WM_TRANS_1(pipe), _PLANE_WM_TRANS_2(pipe))) > > /* define the Watermark register on Ironlake */ > -#define WM0_PIPEA_ILK _MMIO(0x45100) > +#define _WM0_PIPEA_ILK 0x45100 > +#define _WM0_PIPEB_ILK 0x45104 > +#define _WM0_PIPEC_IVB 0x45200 > +#define WM0_PIPE_ILK(pipe) _MMIO_PIPE3((pipe), _WM0_PIPEA_ILK, \ > + _WM0_PIPEB_ILK, _WM0_PIPEC_IVB) > #define WM0_PIPE_PLANE_MASK (0xffff << 16) > #define WM0_PIPE_PLANE_SHIFT 16 > #define WM0_PIPE_SPRITE_MASK (0xff << 8) > #define WM0_PIPE_SPRITE_SHIFT 8 > #define WM0_PIPE_CURSOR_MASK (0xff) > - > -#define WM0_PIPEB_ILK _MMIO(0x45104) > -#define WM0_PIPEC_IVB _MMIO(0x45200) > #define WM1_LP_ILK _MMIO(0x45108) > #define WM1_LP_SR_EN (1 << 31) > #define WM1_LP_LATENCY_SHIFT 24 > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c > index 6ebde7bbac4e..46f8c8728847 100644 > --- a/drivers/gpu/drm/i915/intel_pm.c > +++ b/drivers/gpu/drm/i915/intel_pm.c > @@ -3555,11 +3555,11 @@ static void ilk_write_wm_values(struct > drm_i915_private *dev_priv, > _ilk_disable_lp_wm(dev_priv, dirty); > > if (dirty & WM_DIRTY_PIPE(PIPE_A)) > - I915_WRITE(WM0_PIPEA_ILK, results->wm_pipe[0]); > + I915_WRITE(WM0_PIPE_ILK(PIPE_A), results->wm_pipe[0]); > if (dirty & WM_DIRTY_PIPE(PIPE_B)) > - I915_WRITE(WM0_PIPEB_ILK, results->wm_pipe[1]); > + I915_WRITE(WM0_PIPE_ILK(PIPE_B), results->wm_pipe[1]); > if (dirty & WM_DIRTY_PIPE(PIPE_C)) > - I915_WRITE(WM0_PIPEC_IVB, results->wm_pipe[2]); > + I915_WRITE(WM0_PIPE_ILK(PIPE_C), results->wm_pipe[2]); > > if (dirty & WM_DIRTY_LINETIME(PIPE_A)) > I915_WRITE(PIPE_WM_LINETIME(PIPE_A), results->wm_linetime[0]); > @@ -5647,13 +5647,8 @@ static void ilk_pipe_wm_get_hw_state(struct intel_crtc > *crtc) > struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->base.state); > struct ilk_pipe_wm *active = &cstate->wm.ilk.optimal; > enum pipe pipe = crtc->pipe; > - static const i915_reg_t wm0_pipe_reg[] = { > - [PIPE_A] = WM0_PIPEA_ILK, > - [PIPE_B] = WM0_PIPEB_ILK, > - [PIPE_C] = WM0_PIPEC_IVB, > - }; > > - hw->wm_pipe[pipe] = I915_READ(wm0_pipe_reg[pipe]); > + hw->wm_pipe[pipe] = I915_READ(WM0_PIPE_ILK(pipe)); > if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) > hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe)); > > -- > 2.18.1 > > _______________________________________________ > Intel-gfx mailing list > [email protected] > https://lists.freedesktop.org/mailman/listinfo/intel-gfx _______________________________________________ Intel-gfx mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/intel-gfx
