From: Ville Syrjälä <[email protected]> The maximum watermark value we can ever have on ilk-bdw is 11 bits. Thus we can safely store all of these values in u16.
Also toss in a few s/uint16_t/u16/ etc. while at it. Signed-off-by: Ville Syrjälä <[email protected]> --- drivers/gpu/drm/i915/i915_drv.h | 16 ++--- drivers/gpu/drm/i915/intel_drv.h | 2 +- drivers/gpu/drm/i915/intel_pm.c | 101 +++++++++++++++---------------- 3 files changed, 58 insertions(+), 61 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index e70707e79386..9264fd1b8662 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -1031,17 +1031,17 @@ enum intel_ddb_partitioning { struct intel_wm_level { bool enable; - uint32_t pri_val; - uint32_t spr_val; - uint32_t cur_val; - uint32_t fbc_val; + u16 pri_val; + u16 spr_val; + u16 cur_val; + u16 fbc_val; }; struct ilk_wm_values { - uint32_t wm_pipe[3]; - uint32_t wm_lp[3]; - uint32_t wm_lp_spr[3]; - uint32_t wm_linetime[3]; + u32 wm_pipe[3]; + u32 wm_lp[3]; + u32 wm_lp_spr[3]; + u32 wm_linetime[3]; bool enable_fbc_wm; enum intel_ddb_partitioning partitioning; }; diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h index d08f08f607dd..09abc1035335 100644 --- a/drivers/gpu/drm/i915/intel_drv.h +++ b/drivers/gpu/drm/i915/intel_drv.h @@ -630,7 +630,7 @@ struct intel_crtc_scaler_state { struct intel_pipe_wm { struct intel_wm_level wm[5]; - uint32_t linetime; + u32 linetime; bool fbc_wm_enabled; bool pipe_enabled; bool sprites_enabled; diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 6d074f2e69d3..f23ea4631f9b 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -1188,9 +1188,9 @@ static bool g4x_raw_fbc_wm_set(struct intel_crtc_state *crtc_state, return dirty; } -static uint32_t ilk_compute_fbc_wm(const struct intel_crtc_state *cstate, - const struct intel_plane_state *pstate, - uint32_t pri_val); +static u16 ilk_compute_fbc_wm(const struct intel_crtc_state *cstate, + const struct intel_plane_state *pstate, + u16 pri_val); static bool g4x_raw_plane_wm_compute(struct intel_crtc_state *crtc_state, const struct intel_plane_state *plane_state) @@ -2436,7 +2436,7 @@ static unsigned int ilk_wm_method1(unsigned int pixel_rate, ret = intel_wm_method1(pixel_rate, cpp, latency); ret = DIV_ROUND_UP(ret, 64) + 2; - return ret; + return min_t(unsigned int, ret, USHRT_MAX); } /* latency must be in 0.1us units. */ @@ -2452,11 +2452,11 @@ static unsigned int ilk_wm_method2(unsigned int pixel_rate, width, cpp, latency); ret = DIV_ROUND_UP(ret, 64) + 2; - return ret; + return min_t(unsigned int, ret, USHRT_MAX); } -static uint32_t ilk_wm_fbc(uint32_t pri_val, uint32_t horiz_pixels, - uint8_t cpp) +static u16 ilk_wm_fbc(u16 pri_val, unsigned int horiz_pixels, + unsigned int cpp) { /* * Neither of these should be possible since this function shouldn't be @@ -2473,26 +2473,26 @@ static uint32_t ilk_wm_fbc(uint32_t pri_val, uint32_t horiz_pixels, } struct ilk_wm_maximums { - uint16_t pri; - uint16_t spr; - uint16_t cur; - uint16_t fbc; + u16 pri; + u16 spr; + u16 cur; + u16 fbc; }; /* * For both WM_PIPE and WM_LP. * mem_value must be in 0.1us units. */ -static uint32_t ilk_compute_pri_wm(const struct intel_crtc_state *cstate, - const struct intel_plane_state *pstate, - uint32_t mem_value, - bool is_lp) +static u16 ilk_compute_pri_wm(const struct intel_crtc_state *cstate, + const struct intel_plane_state *pstate, + unsigned int mem_value, + bool is_lp) { - uint32_t method1, method2; + u16 method1, method2; int cpp; if (mem_value == 0) - return U32_MAX; + return U16_MAX; if (!intel_wm_plane_visible(cstate, pstate)) return 0; @@ -2516,15 +2516,15 @@ static uint32_t ilk_compute_pri_wm(const struct intel_crtc_state *cstate, * For both WM_PIPE and WM_LP. * mem_value must be in 0.1us units. */ -static uint32_t ilk_compute_spr_wm(const struct intel_crtc_state *cstate, - const struct intel_plane_state *pstate, - uint32_t mem_value) +static u16 ilk_compute_spr_wm(const struct intel_crtc_state *cstate, + const struct intel_plane_state *pstate, + unsigned int mem_value) { - uint32_t method1, method2; + u16 method1, method2; int cpp; if (mem_value == 0) - return U32_MAX; + return U16_MAX; if (!intel_wm_plane_visible(cstate, pstate)) return 0; @@ -2543,14 +2543,14 @@ static uint32_t ilk_compute_spr_wm(const struct intel_crtc_state *cstate, * For both WM_PIPE and WM_LP. * mem_value must be in 0.1us units. */ -static uint32_t ilk_compute_cur_wm(const struct intel_crtc_state *cstate, - const struct intel_plane_state *pstate, - uint32_t mem_value) +static u16 ilk_compute_cur_wm(const struct intel_crtc_state *cstate, + const struct intel_plane_state *pstate, + unsigned int mem_value) { int cpp; if (mem_value == 0) - return U32_MAX; + return U16_MAX; if (!intel_wm_plane_visible(cstate, pstate)) return 0; @@ -2563,9 +2563,9 @@ static uint32_t ilk_compute_cur_wm(const struct intel_crtc_state *cstate, } /* Only for WM_LP. */ -static uint32_t ilk_compute_fbc_wm(const struct intel_crtc_state *cstate, - const struct intel_plane_state *pstate, - uint32_t pri_val) +static u16 ilk_compute_fbc_wm(const struct intel_crtc_state *cstate, + const struct intel_plane_state *pstate, + u16 pri_val) { int cpp; @@ -2577,8 +2577,7 @@ static uint32_t ilk_compute_fbc_wm(const struct intel_crtc_state *cstate, return ilk_wm_fbc(pri_val, drm_rect_width(&pstate->base.dst), cpp); } -static unsigned int -ilk_display_fifo_size(const struct drm_i915_private *dev_priv) +static u16 ilk_display_fifo_size(const struct drm_i915_private *dev_priv) { if (INTEL_GEN(dev_priv) >= 8) return 3072; @@ -2588,9 +2587,8 @@ ilk_display_fifo_size(const struct drm_i915_private *dev_priv) return 512; } -static unsigned int -ilk_plane_wm_reg_max(const struct drm_i915_private *dev_priv, - int level, bool is_sprite) +static u16 ilk_plane_wm_reg_max(const struct drm_i915_private *dev_priv, + int level, bool is_sprite) { if (INTEL_GEN(dev_priv) >= 8) /* BDW primary/sprite plane watermarks */ @@ -2606,8 +2604,7 @@ ilk_plane_wm_reg_max(const struct drm_i915_private *dev_priv, return level == 0 ? 63 : 255; } -static unsigned int -ilk_cursor_wm_reg_max(const struct drm_i915_private *dev_priv, int level) +static u16 ilk_cursor_wm_reg_max(const struct drm_i915_private *dev_priv, int level) { if (INTEL_GEN(dev_priv) >= 7) return level == 0 ? 63 : 255; @@ -2615,7 +2612,7 @@ ilk_cursor_wm_reg_max(const struct drm_i915_private *dev_priv, int level) return level == 0 ? 31 : 63; } -static unsigned int ilk_fbc_wm_reg_max(const struct drm_i915_private *dev_priv) +static u16 ilk_fbc_wm_reg_max(const struct drm_i915_private *dev_priv) { if (INTEL_GEN(dev_priv) >= 8) return 31; @@ -2624,13 +2621,13 @@ static unsigned int ilk_fbc_wm_reg_max(const struct drm_i915_private *dev_priv) } /* Calculate the maximum primary/sprite plane watermark */ -static unsigned int ilk_plane_wm_max(const struct drm_i915_private *dev_priv, - int level, - const struct intel_wm_config *config, - enum intel_ddb_partitioning ddb_partitioning, - bool is_sprite) +static u16 ilk_plane_wm_max(const struct drm_i915_private *dev_priv, + int level, + const struct intel_wm_config *config, + enum intel_ddb_partitioning ddb_partitioning, + bool is_sprite) { - unsigned int fifo_size = ilk_display_fifo_size(dev_priv); + u16 fifo_size = ilk_display_fifo_size(dev_priv); /* if sprites aren't enabled, sprites get nothing */ if (is_sprite && !config->sprites_enabled) @@ -2665,9 +2662,9 @@ static unsigned int ilk_plane_wm_max(const struct drm_i915_private *dev_priv, } /* Calculate the maximum cursor plane watermark */ -static unsigned int ilk_cursor_wm_max(const struct drm_i915_private *dev_priv, - int level, - const struct intel_wm_config *config) +static u16 ilk_cursor_wm_max(const struct drm_i915_private *dev_priv, + int level, + const struct intel_wm_config *config) { /* HSW LP1+ watermarks w/ multiple pipes */ if (level > 0 && config->num_pipes_active > 1) @@ -2731,9 +2728,9 @@ static bool ilk_validate_wm_level(int level, DRM_DEBUG_KMS("Cursor WM%d too large %u (max %u)\n", level, result->cur_val, max->cur); - result->pri_val = min_t(uint32_t, result->pri_val, max->pri); - result->spr_val = min_t(uint32_t, result->spr_val, max->spr); - result->cur_val = min_t(uint32_t, result->cur_val, max->cur); + result->pri_val = min(result->pri_val, max->pri); + result->spr_val = min(result->spr_val, max->spr); + result->cur_val = min(result->cur_val, max->cur); result->enable = true; } @@ -2749,9 +2746,9 @@ static void ilk_compute_wm_level(const struct drm_i915_private *dev_priv, const struct intel_plane_state *curstate, struct intel_wm_level *result) { - uint16_t pri_latency = dev_priv->wm.pri_latency[level]; - uint16_t spr_latency = dev_priv->wm.spr_latency[level]; - uint16_t cur_latency = dev_priv->wm.cur_latency[level]; + u16 pri_latency = dev_priv->wm.pri_latency[level]; + u16 spr_latency = dev_priv->wm.spr_latency[level]; + u16 cur_latency = dev_priv->wm.cur_latency[level]; /* WM1+ latency values stored in 0.5us units */ if (level > 0) { -- 2.18.1 _______________________________________________ Intel-gfx mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/intel-gfx
