This means moving WaTempDisableDOPClkGating as well. Notice that BXT implements a similar WA to WaProgramL3SqcReg1Default but, according to the BSpec, it does not require WaTempDisableDOPClkGating.
Signed-off-by: Oscar Mateo <[email protected]> Cc: Rodrigo Vivi <[email protected]> Cc: Chris Wilson <[email protected]> Cc: Mika Kuoppala <[email protected]> Cc: Ville Syrjälä <[email protected]> Cc: Imre Deak <[email protected]> --- drivers/gpu/drm/i915/intel_pm.c | 46 +++----------------------------- drivers/gpu/drm/i915/intel_workarounds.c | 44 ++++++++++++++++++++++++++++-- 2 files changed, 45 insertions(+), 45 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 296fe83..74cc2ffe 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -8378,39 +8378,10 @@ static void lpt_suspend_hw(struct drm_i915_private *dev_priv) } } -static void gen8_set_l3sqc_credits(struct drm_i915_private *dev_priv, - int general_prio_credits, - int high_prio_credits) -{ - u32 val; - u32 misccpctl; - - /* WaTempDisableDOPClkGating:bdw */ - misccpctl = I915_READ(GEN7_MISCCPCTL); - I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE); - - val = I915_READ(GEN8_L3SQCREG1); - val &= ~L3_PRIO_CREDITS_MASK; - val |= L3_GENERAL_PRIO_CREDITS(general_prio_credits); - val |= L3_HIGH_PRIO_CREDITS(high_prio_credits); - I915_WRITE(GEN8_L3SQCREG1, val); - - /* - * Wait at least 100 clocks before re-enabling clock gating. - * See the definition of L3SQCREG1 in BSpec. - */ - POSTING_READ(GEN8_L3SQCREG1); - udelay(1); - I915_WRITE(GEN7_MISCCPCTL, misccpctl); -} - static void bdw_init_clock_gating(struct drm_i915_private *dev_priv) { ilk_init_lp_watermarks(dev_priv); - /* WaProgramL3SqcReg1Default:bdw */ - gen8_set_l3sqc_credits(dev_priv, 30, 2); - lpt_init_clock_gating(dev_priv); } @@ -8645,16 +8616,6 @@ static void vlv_init_clock_gating(struct drm_i915_private *dev_priv) I915_WRITE(VLV_GUNIT_CLOCK_GATE, GCFG_DIS); } -static void chv_init_clock_gating(struct drm_i915_private *dev_priv) -{ - /* - * WaProgramL3SqcReg1Default:chv - * See gfxspecs/Related Documents/Performance Guide/ - * LSQC Setting Recommendations. - */ - gen8_set_l3sqc_credits(dev_priv, 38, 2); -} - static void g4x_init_clock_gating(struct drm_i915_private *dev_priv) { uint32_t dspclk_gate; @@ -8782,13 +8743,12 @@ static void nop_init_clock_gating(struct drm_i915_private *dev_priv) void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv) { if (IS_CANNONLAKE(dev_priv) || IS_COFFEELAKE(dev_priv) || - IS_GEMINILAKE(dev_priv) || IS_KABYLAKE(dev_priv) || - IS_BROXTON(dev_priv) || IS_SKYLAKE(dev_priv)) + IS_GEMINILAKE(dev_priv) || IS_KABYLAKE(dev_priv) || + IS_BROXTON(dev_priv) || IS_SKYLAKE(dev_priv) || + IS_CHERRYVIEW(dev_priv)) dev_priv->display.init_clock_gating = nop_init_clock_gating; else if (IS_BROADWELL(dev_priv)) dev_priv->display.init_clock_gating = bdw_init_clock_gating; - else if (IS_CHERRYVIEW(dev_priv)) - dev_priv->display.init_clock_gating = chv_init_clock_gating; else if (IS_HASWELL(dev_priv)) dev_priv->display.init_clock_gating = hsw_init_clock_gating; else if (IS_IVYBRIDGE(dev_priv)) diff --git a/drivers/gpu/drm/i915/intel_workarounds.c b/drivers/gpu/drm/i915/intel_workarounds.c index ca9d906..136f6fb 100644 --- a/drivers/gpu/drm/i915/intel_workarounds.c +++ b/drivers/gpu/drm/i915/intel_workarounds.c @@ -517,11 +517,33 @@ static void mmio_workarounds_apply(struct drm_i915_private *dev_priv, struct i915_wa_reg *wa, u32 count) { + u32 misccpctl; + u32 value; int i; for (i = 0; i < count; i++) { - u32 value = I915_READ(wa[i].addr); + /* WaTempDisableDOPClkGating */ + if ((IS_BROADWELL(dev_priv) || IS_CHERRYVIEW(dev_priv)) && + i915_mmio_reg_equal(wa[i].addr, GEN8_L3SQCREG1)) { + misccpctl = I915_READ(GEN7_MISCCPCTL); + I915_WRITE(GEN7_MISCCPCTL, + misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE); + } + + value = I915_READ(wa[i].addr); I915_WRITE(wa[i].addr, (value & ~wa[i].mask) | wa[i].value); + + /* WaTempDisableDOPClkGating */ + if ((IS_BROADWELL(dev_priv) || IS_CHERRYVIEW(dev_priv)) && + i915_mmio_reg_equal(wa[i].addr, GEN8_L3SQCREG1)) { + /* + * Wait at least 100 clocks before re-enabling clock + * gating See the definition of L3SQCREG1 in BSpec. + */ + POSTING_READ(GEN8_L3SQCREG1); + udelay(1); + I915_WRITE(GEN7_MISCCPCTL, misccpctl); + } } } @@ -582,6 +604,14 @@ static int bdw_gt_workarounds_init(struct drm_i915_private *dev_priv) GT_WA_SET_FIELD(HSW_GTT_CACHE_EN, 0xFFFFFFFF, can_use_gtt_cache ? GTT_CACHE_EN_ALL : 0); + /* + * WaProgramL3SqcReg1Default:bdw + * See "gfxspecs/Related Documents/Performance Guide/LSQC Setting + * Recommendations" and also WaTempDisableDOPClkGating. + */ + GT_WA_SET_FIELD(GEN8_L3SQCREG1, L3_PRIO_CREDITS_MASK, + L3_GENERAL_PRIO_CREDITS(30) | L3_HIGH_PRIO_CREDITS(2)); + return 0; } @@ -602,6 +632,14 @@ static int chv_gt_workarounds_init(struct drm_i915_private *dev_priv) */ GT_WA_SET_FIELD(HSW_GTT_CACHE_EN, 0xFFFFFFFF, GTT_CACHE_EN_ALL); + /* + * WaProgramL3SqcReg1Default:chv + * See "gfxspecs/Related Documents/Performance Guide/LSQC Setting + * Recommendations" and also WaTempDisableDOPClkGating. + */ + GT_WA_SET_FIELD(GEN8_L3SQCREG1, L3_PRIO_CREDITS_MASK, + L3_GENERAL_PRIO_CREDITS(38) | L3_HIGH_PRIO_CREDITS(2)); + return 0; } @@ -686,7 +724,9 @@ static int bxt_gt_workarounds_init(struct drm_i915_private *dev_priv) GEN9_POOLED_EU_LOAD_BALANCING_FIX_DISABLE); } - /* WaProgramL3SqcReg1DefaultForPerf:bxt */ + /* + * WaProgramL3SqcReg1DefaultForPerf:bxt + */ if (IS_BXT_REVID(dev_priv, BXT_REVID_B0, REVID_FOREVER)) GT_WA_SET_FIELD(GEN8_L3SQCREG1, L3_PRIO_CREDITS_MASK, L3_GENERAL_PRIO_CREDITS(62) | -- 1.9.1 _______________________________________________ Intel-gfx mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/intel-gfx
