Am Donnerstag, den 17.02.2011, 10:40 -0800 schrieb Jesse Barnes: > In a few places I replaced reads of per-pipe registers with the actual > register offsets themselves (converting I915_READ(reg) to _PIPE(reg)). > Alexey caught this on his 9xx machine because the cursor control write > was affected. A quick audit showed a few more places where I'd borked > a read, so here's a patch to fix things up.
Tested-by: Alexey Fisher <[email protected]> > Reported-by: Alexey Fisher <[email protected]> > Signed-off-by: Jesse Barnes <[email protected]> > > diff --git a/drivers/gpu/drm/i915/intel_display.c > b/drivers/gpu/drm/i915/intel_display.c > index 0dc5c6f..eadb4b8 100644 > --- a/drivers/gpu/drm/i915/intel_display.c > +++ b/drivers/gpu/drm/i915/intel_display.c > @@ -5291,7 +5291,7 @@ static void i9xx_update_cursor(struct drm_crtc *crtc, > u32 base) > bool visible = base != 0; > > if (intel_crtc->cursor_visible != visible) { > - uint32_t cntl = CURCNTR(pipe); > + uint32_t cntl = I915_READ(CURCNTR(pipe)); > if (base) { > cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT); > cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE; > @@ -5661,7 +5661,7 @@ static int intel_crtc_clock_get(struct drm_device *dev, > struct drm_crtc *crtc) > struct drm_i915_private *dev_priv = dev->dev_private; > struct intel_crtc *intel_crtc = to_intel_crtc(crtc); > int pipe = intel_crtc->pipe; > - u32 dpll = DPLL(pipe); > + u32 dpll = I915_READ(DPLL(pipe)); > u32 fp; > intel_clock_t clock; > > @@ -5749,10 +5749,10 @@ struct drm_display_mode *intel_crtc_mode_get(struct > drm_device *dev, > struct intel_crtc *intel_crtc = to_intel_crtc(crtc); > int pipe = intel_crtc->pipe; > struct drm_display_mode *mode; > - int htot = HTOTAL(pipe); > - int hsync = HSYNC(pipe); > - int vtot = VTOTAL(pipe); > - int vsync = VSYNC(pipe); > + int htot = I915_READ(HTOTAL(pipe)); > + int hsync = I915_READ(HSYNC(pipe)); > + int vtot = I915_READ(VTOTAL(pipe)); > + int vsync = I915_READ(VSYNC(pipe)); > > mode = kzalloc(sizeof(*mode), GFP_KERNEL); > if (!mode) -- Regards, Alexey _______________________________________________ Intel-gfx mailing list [email protected] http://lists.freedesktop.org/mailman/listinfo/intel-gfx
