Since, with GPU-on-package, it's hard to talk about a model number for a specific chipset like 855GM, just use the platform names.
Signed-off-by: Adam Jackson <[email protected]> --- src/i965_render.c | 6 +++--- src/i965_video.c | 4 ++-- src/intel_driver.h | 28 ++++++++++++++-------------- src/intel_module.c | 40 ++++++++++++++++++++-------------------- src/legacy/i810/i810_reg.h | 32 ++++++++++++++++---------------- src/xvmc/xvmc_vld.c | 4 ++-- 6 files changed, 57 insertions(+), 57 deletions(-) diff --git a/src/i965_render.c b/src/i965_render.c index b1ac6ba..e42a8c4 100644 --- a/src/i965_render.c +++ b/src/i965_render.c @@ -401,7 +401,7 @@ static const uint32_t ps_kernel_masknoca_projective_static[][4] = { #include "exa_wm_write.g4b" }; -/* new programs for IGDNG */ +/* new programs for Ironlake */ static const uint32_t sf_kernel_static_gen5[][4] = { #include "exa_sf.g4b.gen5" }; @@ -993,7 +993,7 @@ static drm_intel_bo *gen4_create_wm_state(ScrnInfoPtr scrn, } /* binding table entry count is only used for prefetching, and it has to - * be set 0 for IGDNG + * be set 0 for Ironlake */ if (IS_GEN5(intel)) wm_state->thread1.binding_table_entry_count = 0; @@ -1386,7 +1386,7 @@ static void i965_emit_composite_state(ScrnInfoPtr scrn) if (IS_GEN5(intel)) { /* * The reason to add this extra vertex element in the header is that - * IGDNG has different vertex header definition and origin method to + * Ironlake has different vertex header definition and origin method to * set destination element offset doesn't exist anymore, which means * hardware requires a predefined vertex element layout. * diff --git a/src/i965_video.c b/src/i965_video.c index e16a575..38c8100 100644 --- a/src/i965_video.c +++ b/src/i965_video.c @@ -113,7 +113,7 @@ static const uint32_t ps_kernel_planar_static[][4] = { #include "exa_wm_write.g4b" }; -/* new program for IGDNG */ +/* new program for Ironlake */ static const uint32_t sf_kernel_static_gen5[][4] = { #include "exa_sf.g4b.gen5" }; @@ -675,7 +675,7 @@ static drm_intel_bo *i965_create_wm_state(ScrnInfoPtr scrn, wm_state->thread1.binding_table_entry_count = 7; /* binding table entry count is only used for prefetching, and it has to - * be set 0 for IGDNG + * be set 0 for Ironlake */ if (IS_GEN5(intel)) wm_state->thread1.binding_table_entry_count = 0; diff --git a/src/intel_driver.h b/src/intel_driver.h index be8ec5f..d7f5dfa 100644 --- a/src/intel_driver.h +++ b/src/intel_driver.h @@ -76,11 +76,11 @@ #define PCI_CHIP_I945_GME_BRIDGE 0x27AC #endif -#ifndef PCI_CHIP_IGD_GM -#define PCI_CHIP_IGD_GM 0xA011 -#define PCI_CHIP_IGD_GM_BRIDGE 0xA010 -#define PCI_CHIP_IGD_G 0xA001 -#define PCI_CHIP_IGD_G_BRIDGE 0xA000 +#ifndef PCI_CHIP_PINEVIEW_M +#define PCI_CHIP_PINEVIEW_M 0xA011 +#define PCI_CHIP_PINEVIEW_M_BRIDGE 0xA010 +#define PCI_CHIP_PINEVIEW_G 0xA001 +#define PCI_CHIP_PINEVIEW_G_BRIDGE 0xA000 #endif #ifndef PCI_CHIP_G35_G @@ -133,9 +133,9 @@ #define PCI_CHIP_GM45_BRIDGE 0x2A40 #endif -#ifndef PCI_CHIP_IGD_E_G -#define PCI_CHIP_IGD_E_G 0x2E02 -#define PCI_CHIP_IGD_E_G_BRIDGE 0x2E00 +#ifndef PCI_CHIP_G45_E_G +#define PCI_CHIP_G45_E_G 0x2E02 +#define PCI_CHIP_G45_E_G_BRIDGE 0x2E00 #endif #ifndef PCI_CHIP_G45_G @@ -163,14 +163,14 @@ #define PCI_CHIP_B43_G1_BRIDGE 0x2E90 #endif -#ifndef PCI_CHIP_IGDNG_D_G -#define PCI_CHIP_IGDNG_D_G 0x0042 -#define PCI_CHIP_IGDNG_D_G_BRIDGE 0x0040 +#ifndef PCI_CHIP_IRONLAKE_D_G +#define PCI_CHIP_IRONLAKE_D_G 0x0042 +#define PCI_CHIP_IRONLAKE_D_G_BRIDGE 0x0040 #endif -#ifndef PCI_CHIP_IGDNG_M_G -#define PCI_CHIP_IGDNG_M_G 0x0046 -#define PCI_CHIP_IGDNG_M_G_BRIDGE 0x0044 +#ifndef PCI_CHIP_IRONLAKE_M_G +#define PCI_CHIP_IRONLAKE_M_G 0x0046 +#define PCI_CHIP_IRONLAKE_M_G_BRIDGE 0x0044 #endif #ifndef PCI_CHIP_SANDYBRIDGE_BRIDGE diff --git a/src/intel_module.c b/src/intel_module.c index 528ecf4..f6cc6d4 100644 --- a/src/intel_module.c +++ b/src/intel_module.c @@ -87,8 +87,8 @@ static const SymTabRec _intel_chipsets[] = { {PCI_CHIP_I945_G, "945G"}, {PCI_CHIP_I945_GM, "945GM"}, {PCI_CHIP_I945_GME, "945GME"}, - {PCI_CHIP_IGD_GM, "Pineview GM"}, - {PCI_CHIP_IGD_G, "Pineview G"}, + {PCI_CHIP_PINEVIEW_M, "Pineview GM"}, + {PCI_CHIP_PINEVIEW_G, "Pineview G"}, {PCI_CHIP_I965_G, "965G"}, {PCI_CHIP_G35_G, "G35"}, {PCI_CHIP_I965_Q, "965Q"}, @@ -99,14 +99,14 @@ static const SymTabRec _intel_chipsets[] = { {PCI_CHIP_Q35_G, "Q35"}, {PCI_CHIP_Q33_G, "Q33"}, {PCI_CHIP_GM45_GM, "GM45"}, - {PCI_CHIP_IGD_E_G, "4 Series"}, + {PCI_CHIP_G45_E_G, "4 Series"}, {PCI_CHIP_G45_G, "G45/G43"}, {PCI_CHIP_Q45_G, "Q45/Q43"}, {PCI_CHIP_G41_G, "G41"}, {PCI_CHIP_B43_G, "B43"}, {PCI_CHIP_B43_G1, "B43"}, - {PCI_CHIP_IGDNG_D_G, "Clarkdale"}, - {PCI_CHIP_IGDNG_M_G, "Arrandale"}, + {PCI_CHIP_IRONLAKE_D_G, "Clarkdale"}, + {PCI_CHIP_IRONLAKE_M_G, "Arrandale"}, {PCI_CHIP_SANDYBRIDGE_GT1, "Sandybridge" }, {PCI_CHIP_SANDYBRIDGE_GT2, "Sandybridge" }, {PCI_CHIP_SANDYBRIDGE_GT2_PLUS, "Sandybridge" }, @@ -137,8 +137,8 @@ static const struct pci_id_match intel_device_match[] = { INTEL_DEVICE_MATCH (PCI_CHIP_I945_G, 0 ), INTEL_DEVICE_MATCH (PCI_CHIP_I945_GM, 0 ), INTEL_DEVICE_MATCH (PCI_CHIP_I945_GME, 0 ), - INTEL_DEVICE_MATCH (PCI_CHIP_IGD_GM, 0 ), - INTEL_DEVICE_MATCH (PCI_CHIP_IGD_G, 0 ), + INTEL_DEVICE_MATCH (PCI_CHIP_PINEVIEW_M, 0 ), + INTEL_DEVICE_MATCH (PCI_CHIP_PINEVIEW_G, 0 ), INTEL_DEVICE_MATCH (PCI_CHIP_I965_G, 0 ), INTEL_DEVICE_MATCH (PCI_CHIP_G35_G, 0 ), INTEL_DEVICE_MATCH (PCI_CHIP_I965_Q, 0 ), @@ -149,13 +149,13 @@ static const struct pci_id_match intel_device_match[] = { INTEL_DEVICE_MATCH (PCI_CHIP_Q35_G, 0 ), INTEL_DEVICE_MATCH (PCI_CHIP_Q33_G, 0 ), INTEL_DEVICE_MATCH (PCI_CHIP_GM45_GM, 0 ), - INTEL_DEVICE_MATCH (PCI_CHIP_IGD_E_G, 0 ), + INTEL_DEVICE_MATCH (PCI_CHIP_G45_E_G, 0 ), INTEL_DEVICE_MATCH (PCI_CHIP_G45_G, 0 ), INTEL_DEVICE_MATCH (PCI_CHIP_Q45_G, 0 ), INTEL_DEVICE_MATCH (PCI_CHIP_G41_G, 0 ), INTEL_DEVICE_MATCH (PCI_CHIP_B43_G, 0 ), - INTEL_DEVICE_MATCH (PCI_CHIP_IGDNG_D_G, 0 ), - INTEL_DEVICE_MATCH (PCI_CHIP_IGDNG_M_G, 0 ), + INTEL_DEVICE_MATCH (PCI_CHIP_IRONLAKE_D_G, 0 ), + INTEL_DEVICE_MATCH (PCI_CHIP_IRONLAKE_M_G, 0 ), INTEL_DEVICE_MATCH (PCI_CHIP_SANDYBRIDGE_GT1, 0 ), INTEL_DEVICE_MATCH (PCI_CHIP_SANDYBRIDGE_GT2, 0 ), INTEL_DEVICE_MATCH (PCI_CHIP_SANDYBRIDGE_GT2_PLUS, 0 ), @@ -182,8 +182,8 @@ static PciChipsets intel_pci_chipsets[] = { {PCI_CHIP_I945_G, PCI_CHIP_I945_G, NULL}, {PCI_CHIP_I945_GM, PCI_CHIP_I945_GM, NULL}, {PCI_CHIP_I945_GME, PCI_CHIP_I945_GME, NULL}, - {PCI_CHIP_IGD_GM, PCI_CHIP_IGD_GM, NULL}, - {PCI_CHIP_IGD_G, PCI_CHIP_IGD_G, NULL}, + {PCI_CHIP_PINEVIEW_M, PCI_CHIP_PINEVIEW_M, NULL}, + {PCI_CHIP_PINEVIEW_G, PCI_CHIP_PINEVIEW_G, NULL}, {PCI_CHIP_I965_G, PCI_CHIP_I965_G, NULL}, {PCI_CHIP_G35_G, PCI_CHIP_G35_G, NULL}, {PCI_CHIP_I965_Q, PCI_CHIP_I965_Q, NULL}, @@ -194,13 +194,13 @@ static PciChipsets intel_pci_chipsets[] = { {PCI_CHIP_Q35_G, PCI_CHIP_Q35_G, NULL}, {PCI_CHIP_Q33_G, PCI_CHIP_Q33_G, NULL}, {PCI_CHIP_GM45_GM, PCI_CHIP_GM45_GM, NULL}, - {PCI_CHIP_IGD_E_G, PCI_CHIP_IGD_E_G, NULL}, + {PCI_CHIP_G45_E_G, PCI_CHIP_G45_E_G, NULL}, {PCI_CHIP_G45_G, PCI_CHIP_G45_G, NULL}, {PCI_CHIP_Q45_G, PCI_CHIP_Q45_G, NULL}, {PCI_CHIP_G41_G, PCI_CHIP_G41_G, NULL}, {PCI_CHIP_B43_G, PCI_CHIP_B43_G, NULL}, - {PCI_CHIP_IGDNG_D_G, PCI_CHIP_IGDNG_D_G, NULL}, - {PCI_CHIP_IGDNG_M_G, PCI_CHIP_IGDNG_M_G, NULL}, + {PCI_CHIP_IRONLAKE_D_G, PCI_CHIP_IRONLAKE_D_G, NULL}, + {PCI_CHIP_IRONLAKE_M_G, PCI_CHIP_IRONLAKE_M_G, NULL}, {PCI_CHIP_SANDYBRIDGE_GT1, PCI_CHIP_SANDYBRIDGE_GT1, NULL}, {PCI_CHIP_SANDYBRIDGE_GT2, PCI_CHIP_SANDYBRIDGE_GT2, NULL}, {PCI_CHIP_SANDYBRIDGE_GT2_PLUS, PCI_CHIP_SANDYBRIDGE_GT2_PLUS, NULL}, @@ -301,11 +301,11 @@ void intel_detect_chipset(ScrnInfoPtr scrn, chipset->name = "945GME"; chipset->info = &intel_i915_info; break; - case PCI_CHIP_IGD_GM: + case PCI_CHIP_PINEVIEW_M: chipset->name = "Pineview GM"; chipset->info = &intel_g33_info; break; - case PCI_CHIP_IGD_G: + case PCI_CHIP_PINEVIEW_G: chipset->name = "Pineview G"; chipset->info = &intel_g33_info; break; @@ -349,7 +349,7 @@ void intel_detect_chipset(ScrnInfoPtr scrn, chipset->name = "GM45"; chipset->info = &intel_g4x_info; break; - case PCI_CHIP_IGD_E_G: + case PCI_CHIP_G45_E_G: chipset->name = "4 Series"; chipset->info = &intel_g4x_info; break; @@ -369,11 +369,11 @@ void intel_detect_chipset(ScrnInfoPtr scrn, chipset->name = "B43"; chipset->info = &intel_g4x_info; break; - case PCI_CHIP_IGDNG_D_G: + case PCI_CHIP_IRONLAKE_D_G: chipset->name = "Clarkdale"; chipset->info = &intel_ironlake_info; break; - case PCI_CHIP_IGDNG_M_G: + case PCI_CHIP_IRONLAKE_M_G: chipset->name = "Arrandale"; chipset->info = &intel_ironlake_info; break; diff --git a/src/legacy/i810/i810_reg.h b/src/legacy/i810/i810_reg.h index 2b67934..54faeb3 100644 --- a/src/legacy/i810/i810_reg.h +++ b/src/legacy/i810/i810_reg.h @@ -982,18 +982,18 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. # define DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS 0x003f0000 # define DPLL_FPA01_P1_POST_DIV_SHIFT 16 # define DPLL_FPA01_P1_POST_DIV_SHIFT_IGD 15 -/* IGDNG */ +/* Ironlake */ # define DPLL_FPA0_P1_POST_DIV_SHIFT 16 # define PLL_P2_DIVIDE_BY_4 (1 << 23) /* i830, required in DVO non-gang */ # define PLL_P1_DIVIDE_BY_TWO (1 << 21) /* i830 */ # define PLL_REF_INPUT_DREFCLK (0 << 13) # define PLL_REF_INPUT_TVCLKINA (1 << 13) /* i830 */ -# define PLL_REF_INPUT_SUPER_SSC (1 << 13) /* IGDNG: 120M SSC */ +# define PLL_REF_INPUT_SUPER_SSC (1 << 13) /* Ironlake: 120M SSC */ # define PLL_REF_INPUT_TVCLKINBC (2 << 13) /* SDVO TVCLKIN */ # define PLLB_REF_INPUT_SPREADSPECTRUMIN (3 << 13) # define PLL_REF_INPUT_MASK (3 << 13) -# define PLL_REF_INPUT_DMICLK (5 << 13) /* IGDNG: DMI refclk */ +# define PLL_REF_INPUT_DMICLK (5 << 13) /* Ironlake: DMI refclk */ # define PLL_LOAD_PULSE_PHASE_SHIFT 9 /* * Parallel to Serial Load Pulse phase selection. @@ -1003,7 +1003,7 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ # define PLL_LOAD_PULSE_PHASE_MASK (0xf << PLL_LOAD_PULSE_PHASE_SHIFT) # define DISPLAY_RATE_SELECT_FPA1 (1 << 8) -/* IGDNG */ +/* Ironlake */ # define PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT 9 # define PLL_REF_SDVO_HDMI_MULTIPLIER_MASK (7 << 9) # define PLL_REF_SDVO_HDMI_MULTIPLIER(x) (((x)-1)<< PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) @@ -2157,7 +2157,7 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define PIPEACONF_PIPE_LOCKED (1<<25) #define PIPEACONF_PALETTE 0 #define PIPEACONF_GAMMA (1<<24) -/* IGDNG: gamma */ +/* Ironlake: gamma */ #define PIPECONF_PALETTE_8BIT (0<<24) #define PIPECONF_PALETTE_10BIT (1<<24) #define PIPECONF_PALETTE_12BIT (2<<24) @@ -2165,7 +2165,7 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define PIPECONF_PROGRESSIVE (0 << 21) #define PIPECONF_INTERLACE_W_FIELD_INDICATION (6 << 21) #define PIPECONF_INTERLACE_FIELD_0_ONLY (7 << 21) -/* IGDNG */ +/* Ironlake */ #define PIPECONF_MSA_TIMING_DELAY (0<<18) /* for eDP */ #define PIPECONF_NO_DYNAMIC_RATE_CHANGE (0 << 16) #define PIPECONF_NO_ROTATION (0<<14) @@ -2319,9 +2319,9 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define DISPPLANE_8BPP (0x2<<26) #define DISPPLANE_15_16BPP (0x4<<26) #define DISPPLANE_16BPP (0x5<<26) -#define DISPPLANE_32BPP_NO_ALPHA (0x6<<26) /* IGDNG: BGRX */ -#define DISPPLANE_32BPP (0x7<<26) /* IGDNG: not support */ -/* IGDNG */ +#define DISPPLANE_32BPP_NO_ALPHA (0x6<<26) /* Ironlake: BGRX */ +#define DISPPLANE_32BPP (0x7<<26) /* Ironlake: not support */ +/* Ironlake */ #define DISPPLANE_32BPP_10 (0x8<<26) /* 2:10:10:10 */ #define DISPPLANE_32BPP_BGRX (0xa<<26) #define DISPPLANE_64BPP (0xc<<26) @@ -2329,11 +2329,11 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define DISPPLANE_STEREO_ENABLE (1<<25) #define DISPPLANE_STEREO_DISABLE 0 #define DISPPLANE_SEL_PIPE_MASK (1<<24) -#define DISPPLANE_SEL_PIPE_A 0 /* IGDNG: don't use */ +#define DISPPLANE_SEL_PIPE_A 0 /* Ironlake: don't use */ #define DISPPLANE_SEL_PIPE_B (1<<24) #define DISPPLANE_NORMAL_RANGE (0<<25) #define DISPPLANE_EXT_RANGE (1<<25) -/* IGDNG */ +/* Ironlake */ #define DISPPLANE_CSC_BYPASS (0<<24) #define DISPPLANE_CSC_PASSTHROUGH (1<<24) #define DISPPLANE_SRC_KEY_ENABLE (1<<22) @@ -2347,17 +2347,17 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define DISPPLANE_ALPHA_TRANS_DISABLE 0 #define DISPPLANE_SPRITE_ABOVE_DISPLAYA 0 #define DISPPLANE_SPRITE_ABOVE_OVERLAY (1) -/* IGDNG */ +/* Ironlake */ #define DISPPLANE_X_TILE (1<<10) #define DISPPLANE_LINEAR (0<<10) #define DSPABASE 0x70184 -/* IGDNG */ +/* Ironlake */ #define DSPALINOFF 0x70184 #define DSPASTRIDE 0x70188 #define DSPBBASE 0x71184 -/* IGDNG */ +/* Ironlake */ #define DSPBLINOFF 0x71184 #define DSPBADDR DSPBBASE #define DSPBSTRIDE 0x71188 @@ -2721,7 +2721,7 @@ typedef enum { #define MCHBAR_RENDER_STANDBY 0x111B8 #define RENDER_STANDBY_ENABLE (1 << 30) -/* IGDNG */ +/* Ironlake */ /* warmup time in us */ #define WARMUP_PCH_REF_CLK_SSC_MOD 1 @@ -3054,7 +3054,7 @@ typedef enum { #define FDI_DP_PORT_WIDTH_X3 (2<<19) #define FDI_DP_PORT_WIDTH_X4 (3<<19) #define FDI_TX_ENHANCE_FRAME_ENABLE (1<<18) -/* IGDNG: hardwired to 1 */ +/* Ironlake: hardwired to 1 */ #define FDI_TX_PLL_ENABLE (1<<14) /* both Tx and Rx */ #define FDI_SCRAMBLING_ENABLE (0<<7) diff --git a/src/xvmc/xvmc_vld.c b/src/xvmc/xvmc_vld.c index d72e105..570e9b6 100644 --- a/src/xvmc/xvmc_vld.c +++ b/src/xvmc/xvmc_vld.c @@ -120,7 +120,7 @@ static uint32_t field_f_b_kernel[][4] = { #include "shader/vld/field_f_b.g4b" }; -/* on IGDNG */ +/* on Ironlake */ static uint32_t lib_kernel_gen5[][4] = { #include "shader/vld/lib.g4b.gen5" }; @@ -186,7 +186,7 @@ static uint32_t field_f_b_kernel_idct[][4] = { #include "shader/mc/field_f_b_igd.g4b" }; -/* on IGDNG */ +/* on Ironlake */ static uint32_t lib_kernel_idct_gen5[][4] = { #include "shader/mc/lib_igd.g4b.gen5" }; -- 1.7.3.5 _______________________________________________ Intel-gfx mailing list [email protected] http://lists.freedesktop.org/mailman/listinfo/intel-gfx
