On Mon, Jul 03, 2017 at 02:56:47PM +0530, rohan sundar wrote: > > The data throughput rate for Rx is ~10 MiB/s, which is half of what is > expected (~20 MiB/s). > > The board is a modification of the Hackrf project, which has an FPGA > instead of the CPLD for onboard baseband processing capabilities. The > project is detailed here <https://github.com/ainnovators/noob-sdr>
Have you ported the existing CPLD function to your FPGA? The CPLD on HackRF One translates between a Double Data Rate 8 bit interface at the sample rate (ADC/DAC) and a Single Data Rate 8 bit interface at twice the sample rate (SGPIO on the LPC4320). Michael _______________________________________________ HackRF-dev mailing list [email protected] https://pairlist9.pair.net/mailman/listinfo/hackrf-dev
