On Mon, 14 Jan 2019 21:34:34 +0100
Tamás Király <[email protected]> wrote:
> I'm simulating the internal clock of an embedded microcontroller...
You can't expect a million interrupts per second and host OS running
simultaneously.
(1us gives some 4k instructions inbetween on recent 3GHz cpu core)
Usual way for emulating hw state machines maintaining RT accuracy:
loop:
1. make a batch "n" of emulated hw instructions that span observable
i/o ops or shared state commits; then
2. count expected 'hw cycles' above batch would need on real hw,
duration "d" of real time it would take then "t" point of time batch
results are due; then
3. set "hw progress" timer P to "t" point
4. "execute" batch "n"
(at full host speed of course, hw logic/instructions are
transpiled to host instruction set)
5. sleep (give cpu to host OS) until P fires
6. commit state (results of batch) "n"
n += 1;
goto loop
Hope this helps,
--
Wojciech S. Czarnecki
<< ^oo^ >> OHIR-RIPE
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