Nilay,
I am editing the M5 memory system and am actually working with Trimaran,
which incorporates the M5 system in something called M5elements. I have
specifically been editing files in Trimaran that make function calls to M5
named send_dcache_request(req) and send_icache_request(req). I have
basically been printing out every request (req.addr, req.type, etc.) and
then counting the amount of stalls till I receive a hit and those that take
> 20 cycles I record as misses and export their information.
I'm sure there is a much more elegant solution where I could just directly
get this information from M5 last level cache (L2), but the cache.cc and
missqueue files do not seem to have that information. I'm hoping that I
could just directly get this information, which would be a better solution.
I hope that clarified my question.
-Daniel
--------------------------------------------------
From: "Nilay Vaish" <[email protected]>
Sent: Friday, May 27, 2011 12:39 PM
To: "Daniel Chang" <[email protected]>
Cc: <[email protected]>
Subject: Re: [gem5-users] Getting accurate L2 Cache Miss Information
(missCycle, Address, Type)
On Fri, 27 May 2011, Daniel Chang wrote:
I am trying to find the last cache miss information so that I can get the
accesses right before they go to the main memory controller. Specifically
when they are sent to the controller (cycle), the type of miss
(read/write) and the address. This is the information needed to make a
DRAMsim trace.
My solution is currently recording all D and I-Cache requests and then
pattern matching the ones that stall > 20 cycles, but that generates a
huge text file. I'd like a more elegant solution since I imagine M5 has
the last cache miss information somewhere, but my search in the "miss"
folder has yielded nothing.
Thanks!
-Daniel
Which memory system are you making use of?
--
Nilay
What I meant was that whether you are making use of the m5 memory system
or the Ruby memory system. Which files have you edited to record the cache
requests?
--
Nilay
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