On Fri, 27 May 2011, Daniel Chang wrote:
I am trying to find the last cache miss information so that I can get
the accesses right before they go to the main memory controller.
Specifically when they are sent to the controller (cycle), the type of
miss (read/write) and the address. This is the information needed to
make a DRAMsim trace.
My solution is currently recording all D and I-Cache requests and then
pattern matching the ones that stall > 20 cycles, but that generates a
huge text file. I'd like a more elegant solution since I imagine M5 has
the last cache miss information somewhere, but my search in the "miss"
folder has yielded nothing.
Thanks!
-Daniel
Which memory system are you making use of?
--
Nilay
What I meant was that whether you are making use of the m5 memory system
or the Ruby memory system. Which files have you edited to record the cache
requests?
--
Nilay
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