Thanks for your email.
I will look into the "multi-level TLB for Arm" implementation

Wish you a good day
Arun


On Thu, May 18, 2023 at 9:25 PM Giacomo Travaglini <
[email protected]> wrote:

> Just for the sake of completeness (I know Arun asked about X86).
> There is a multi-level TLB for Arm; it is possible for other ISAs to
> implement the same, it requires a developer to move the
> translateAtomic/Timing methods from the TLB to the MMU
>
>
>
> Kind Regards
>
>
>
> Giacomo
>
>
>
> *From: *Jason Lowe-Power via gem5-users <[email protected]>
> *Date: *Thursday, 18 May 2023 at 16:38
> *To: *The gem5 Users mailing list <[email protected]>
> *Cc: *Laney Laney <[email protected]>, Arun Kavumkal <
> [email protected]>, Jason Lowe-Power <[email protected]>
> *Subject: *[gem5-users] Re: Multi-level TLB is implemented in performance
>
> There is not a multi-level TLB model in mainline gem5.
>
>
>
> Cheers,
>
> Jason
>
>
>
> On Thu, May 18, 2023 at 5:43 AM Arun Kavumkal via gem5-users <
> [email protected]> wrote:
>
> Hi,
>
> Can anyone please tell me whether a multi-level TLB implementation is
> currently available for x86?
>
>
>
> Thanks
>
> Arun
>
>
>
> On Wed, Oct 28, 2020 at 9:01 PM Jason Lowe-Power via gem5-users <
> [email protected]> wrote:
>
> Yes, this is possible, and I believe it's already implemented for Arm.
>
>
>
> The best place to start is src/arch/<your architecture>/tlb.cc
>
>
>
> Cheers,
>
> Jason
>
>
>
> On Wed, Oct 28, 2020 at 1:27 AM Laney Laney via gem5-users <
> [email protected]> wrote:
>
> Hi,all. I would like to know if it is possible to implement multi-level
> TLB on gem5 performance by modeling the latency of TLB. If so, which files
> or functions should I start with?
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