Hi! I have figured out that synthesis is somehow missing from the open source logic array toolchain. There are ancient tools for silicon, and there are some tools for PALs and GALs, but there is no tool which is targeted to logic arrays and flexible enough to be able to synthesize for CPLDs and FPGAs.
So I started to make one. The logic optimization part is ready. I call it bistromatic, because it may or may not implement the espresso algorithm. I have written it in python, and it needs 22 secs to assemble a four bit full adder from AND, OR and NOT gates on a 1.5Ghz Pentium M. You can download it and read my thoughts surrounding it at http://magwas.rulez.org/BistromaticLogicOptimizationAlgorithmInPython Happy New Year, and thank you for the fish. _______________________________________________ geda-dev mailing list [email protected] http://www.seul.org/cgi-bin/mailman/listinfo/geda-dev
