Hi All, I have heard from time to time that some user/developer claim that gEDA does not support BUS or hierarchy. gEDA already support BUS and hierachy, it is only some backends which have not used the powerful features already within gEDA. Verilog netlister already used such powerful feature.
gEDA, due to its very flexible architecture, already support all kinds of BUS except it has not use the thick net (the visual "BUS") structure in gEDA code. Attached is an example of BUS, none-flat hierarchy, and a "Hier report script" that can generate Hierarchical Verilog Netlist with BUS, and also some other kinds of hier report. Adding the "visual thick BUS" to current gEDA is a plus, but it should in no way reduce its flexibilities. Best Regards, Paul Tan
geda_hier_tools.tar.gz
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