It looks like the machinery that picks MIPS branch-likely instructions (on
processors that don't object to them) is driven purely by their delay slot
annul properties and not at all by branch probability.
That brings up a couple of questions.
1. Assuming it doesn't matter to the delay slot fill logic, does GCC offer a
way for one branch instruction to be picked over another based on branch
probability calculations? I looked a bit and didn't see how to do that.
2. In the delay slot fill machinery (reorg.c), I don't see how a target can
supply hooks to adjust the picking of one branch over another. In other words,
if the architecture has branch-likely that has annul, but that instruction
should not be used in a particular spot because the branch is in fact NOT
likely, how would one do that?
paul
