2009/6/16 Jeff Law <l...@redhat.com>: > Ian Lance Taylor wrote: >> >> daniel tian <daniel.xnt...@gmail.com> writes: >> >> >>> >>> There is a problem I encountered. I port gcc to 32bit RISC. The >>> LOAD/STORE only has 8bit displacement. If the immediate displacement >>> larger than 256, the displacement must be force into register. In >>> addition, if the immediate is larger than 512, it can only move into >>> one specified register R0. >>> >>> Like: >>> >>> LW R2 (R1) #252 ;; means R2 = Mem(R1 + 255) >>> >>> LW R2 (R1) #508;; it is wrong. immediate 508 should force into >>> register first. >>> >>> >>> LW R2 (R1) #0x500;; it is wrong, immediate 0x500 should force into >>> register R0 first. >>> >>> Now, for immediate movement, it is achieved to move large immediate. >>> But I don't know how to make the address mode legitimate. Now I try to >>> add the code in LEGITIMIZE_RELOAD_ADDRESS like sh.md, or arm.md. But >>> cc1 still crashed, when the frame size is larger than 255. Do I miss >>> something? >>> >> >> I would fix this in LEGITIMIZE_RELOAD_ADDRESS or in >> TARGET_SECONDARY_RELOAD. I don't know why cc1 crashed, you will have to >> debug that. >> > > LEGITIMIZE_RELOAD_ADDRESS is not the right place to handle this -- > LEGITIMIZE_RELOAD_ADDRESS is to be used when target specific approaches for > reloading can generate more efficient code than the generic code in reload. > The generic code should be producing correct, though potentially > inefficient code. > > I do agree that the target is going to need secondary reload support. > > jeff >
You mean before LEGITIMIZE_RELOAD_ADDRESS, cc1 must generate the correct RTL code, regardless of whether efficient or not. Take the immediate load for instance, should I generate the the right code in "movm" expander? I mean ,first the larger immediate data will move into a pseduo register, then I insert a RTL code, first move to R0, then R0 move to the pseduo register. Right? Now I just force the larger immedate into a register, and let the reload to move the immediate into R0 register.
