I would appreciate any help in this reload problem
that I have been struggling with for some time:
I completed a gcc back end port to a processor that
supports both displaced and indexed addressing modes
for load, but only displaced for store. For example:
ld.w Rd Rb imm (load from Rb+imm)
ld.w Rd Rb Ri (load from Rb+4*Ri)
st.w Rd Rb imm (store to Rb+imm)
st.w Rd Rb Ri (indexed not allowed for store)
This compiler runs fine, but currently without
generating indexed load instructions.
In order to enable indexed loads, I extended
GO_IF_LEGITIMATE_ADDRESS to also match indexed
addresses, added a memory constraint 'R' to match
nonindexed addresses, and used R for stores in the
'mov' rule (see below). This rule now defines an
explicit case for all address modes, except indexed
stores. I understand that the reloader should convert
these by loading the store address into a register.
This appears not to happen: although indexed load
instructions are now indeed being generated, I get the
following error messages on such stores:
(insn 25 14 15 0 (set (mem/s:SI (plus:SI (mult:SI
(reg:SI 11 a11 [ i ])
(const_int 4 [0x4]))
(reg/f:SI 9 a9 [26])) [3 n S4
A32])
(reg:SI 15 a15)) 2 {movsi} (nil)
(nil))
x.c:6: internal compiler error: in
reload_cse_simplify_operands, at postreload.c:393
Tracing all this in find_reloads (reload.c), I see a
call to find_reloads_address, indeed with reload type
RELOAD_FOR_OUTPUT_ADDRESS, but this function
immediately discovers that the address is a
strict_memory_address, and decides to do nothing. This
leads me to believe that I made some error in the
STRICT case of GO_IF_LEGITIMATE_ADDRESS, but everyting
does look ok there.
Is there anything that I am doing obviously wrong?
------------------------------------------------------
#define GO_IF_LEGITIMATE_ADDRESS ... \
-- recognizes register, displaced, and indexed --
#define EXTRA_CONSTRAINT(X, C) \
( \
...
(C) == 'R' ? ( GET_CODE(X) == MEM \
&& falcon_non_indexed_p( \
XEXP(X,0), GET_MODE(X)\
)) : \
0)
#define EXTRA_MEMORY_CONSTRAINT(X, STR) ((X) == 'R')
(define_insn "mov<mode>"
[(set
(match_operand:BWD 0 "nonimmediate_operand"
"=r,R,r,r,r,r,r,r,x,r")
(match_operand:BWD 1 "general_operand"
"m,r,L,I,Q,n,i,x,r,r"))]
""
"@
%L1<m> %0 %1;
%S0<m> %0 %1;
xor %0 %0;
mv %0 %1;
mv %0 (%1);
mv %0 [EMAIL PROTECTED](%1);\;sethi %0 [EMAIL PROTECTED](%1);
mv %0 [EMAIL PROTECTED](%1);\;sethi %0 [EMAIL PROTECTED](%1);
mv %0 %1;
mv %0 %1;
mv<m> %0 %1;")
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