I collapsed the macro exactly because I am pretty sure
that this macro is ok (I have extensively verified
that it works), and to keep the
initial message small. I have attached my complete
configuration file this time.
--- Dave Korn <[EMAIL PROTECTED]> wrote:
> On 08 June 2006 18:54, Juul Vanderspek wrote:
>
> > Um, this just is a collapse of some large macro.
> > The original compiles into a compiler that refuses
> to
> > reload.
>
>
> The point I was making was that if you think
> there's a problem with that
> macro, and you've posted to the list to ask if
> anyone can help you analyse the
> problem with the macro, then leaving out the vital
> details, such as the macro
> itself, is a bit .... well ... you know.
>
> Debugging by guesswork and ESP is not recommended
> by most textbooks on sound
> engineering practice! Now show us yer code!
>
>
> cheers,
> DaveK
> --
> Can't think of a witty .sigline today....
>
>
__________________________________________________
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/* Definitions for GCC. Part of the machine description for FALCON.
Copyright (C) 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005
Free Software Foundation, Inc.
Contributed by Axis Communications. Written by Hans-Peter Nilsson.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2, or (at your option)
any later version.
GCC is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with GCC; see the file COPYING. If not, write to
the Free Software Foundation, 51 Franklin Street, Fifth Floor,
Boston, MA 02110-1301, USA. */
/* After the first "Node:" comment comes all preprocessor directives and
attached declarations described in the info files, the "Using and
Porting GCC" manual (uapgcc), in the same order as found in the "Target
macros" section in the gcc-2.9x CVS edition of 2000-03-17. FIXME: Not
really, but needs an update anyway.
There is no generic copy-of-uapgcc comment, you'll have to see uapgcc
for that. If applicable, there is a FALCON-specific comment. The order
of macro definitions follow the order in the manual. Every section in
the manual (node in the info pages) has an introductory `Node:
<subchapter>' comment. If no macros are defined for a section, only
the section-comment is present. */
/* Note that other header files (e.g. config/elfos.h, config/linux.h,
config/falcon/linux.h and config/falcon/aout.h) are responsible for lots of
settings not repeated below. This file contains general FALCON
definitions and definitions for the falcon-*-elf subtarget. */
/* We don't want to use gcc_assert for everything, as that can be
compiled out. */
#define FALCON_ASSERT(x) \
do { if (!(x)) internal_error ("FALCON-port assertion failed: " #x); } while
(0)
/* Last register in main register bank r0..r15. */
#define FALCON_LAST_GENERAL_REGISTER 15
/* Descriptions of registers used for arguments. */
/* Note: r15 has a special use in the prologue/epiloque
* of vararg functions (an additional temp),
* so do not add it to the parameter registers.
*/
#define FALCON_FIRST_ARG_REG 10
#define FALCON_MAX_ARGS_IN_REGS 5
#define FALCON_MAX_ARGS_IN_REGSM1 (FALCON_MAX_ARGS_IN_REGS-1)
#define FALCON_FUNCTION_ARG_SIZE(MODE, TYPE) \
((MODE) != BLKmode ? GET_MODE_SIZE (MODE) \
: (unsigned) int_size_in_bytes (TYPE))
/* Changing the order used to be necessary to put the fourth __make_dp
argument (a DImode parameter) in registers, to fit with the libfunc
parameter passing scheme used for intrinsic functions. FIXME: Check
performance and maybe remove definition from TARGET_LIBGCC2_CFLAGS now
that it isn't strictly necessary. We used to do this through
TARGET_LIBGCC2_CFLAGS, but that became increasingly difficult as the
parenthesis (that needed quoting) travels through several layers of
make and shell invocations. */
#ifdef IN_LIBGCC2
#define __make_dp(a,b,c,d) __falcon_make_dp(d,a,b,c)
#endif
/* Node: Driver */
/* When using make with defaults.mak for Sun this will handily remove
any "-target sun*" switches. */
/* We need to override any previous definitions (linux.h) */
#undef WORD_SWITCH_TAKES_ARG
#define WORD_SWITCH_TAKES_ARG(STR) \
(DEFAULT_WORD_SWITCH_TAKES_ARG (STR))
/* Also provide canonical vN definitions when user specifies an alias.*/
#define CPP_SPEC "%(cpp_subtarget)"
/* For the falcon-*-elf subtarget. */
#define FALCON_CPP_SUBTARGET_SPEC ""
/* Remove those Sun-make "target" switches. */
/* Override previous definitions (linux.h). */
#undef CC1_SPEC
#define CC1_SPEC "%(cc1_subtarget)"
/* For the falcon-*-elf subtarget. */
#define FALCON_CC1_SUBTARGET_SPEC ""
#define CC1PLUS_SPEC ""
/* Override previous definitions (linux.h). */
#undef ASM_SPEC
#define ASM_SPEC \
"%{v:-v}\
%(asm_subtarget)"
/* For the falcon-*-elf subtarget. */
#define FALCON_ASM_SUBTARGET_SPEC ""
/* Override previous definitions (svr4.h). */
#undef LINK_SPEC
#define LINK_SPEC \
"%{v:--verbose}\
%(link_subtarget)"
/* For the falcon-*-elf subtarget. */
#define FALCON_LINK_SUBTARGET_SPEC ""
/* Which library to get. The simulator uses a different library for
the low-level syscalls (implementing the Linux syscall ABI instead
of direct-iron accesses). Default everything with the stub "nosys"
library. */
/* Override previous definitions (linux.h). */
#undef LIB_SPEC
#define LIB_SPEC ""
/* Linker startfile options; crt0 flavors.
We need to remove any previous definition (elfos.h). */
#undef STARTFILE_SPEC
#define STARTFILE_SPEC "-u _start"
#undef ENDFILE_SPEC
#define EXTRA_SPECS \
{"cpp_subtarget", FALCON_CPP_SUBTARGET_SPEC}, \
{"cc1_subtarget", FALCON_CC1_SUBTARGET_SPEC}, \
{"asm_subtarget", FALCON_ASM_SUBTARGET_SPEC}, \
{"link_subtarget", FALCON_LINK_SUBTARGET_SPEC}, \
FALCON_SUBTARGET_EXTRA_SPECS
#define FALCON_SUBTARGET_EXTRA_SPECS
/* Node: Run-time Target */
#define TARGET_CPU_CPP_BUILTINS() \
do \
{ \
builtin_define_std ("falcon"); \
builtin_define_std ("FALCON"); \
builtin_define_std ("GNU_FALCON"); \
builtin_assert ("cpu=falcon"); \
builtin_assert ("machine=falcon"); \
} \
while (0)
/* This needs to be at least 32 bits. */
extern int target_flags;
/* Print subsidiary information on the compiler version in use.
Do not use VD.D syntax (D=digit), since this will cause confusion
with the base gcc version among users, when we ask which version of
gcc-falcon they are using. Please use some flavor of "R<number>" for
the version (no need for major.minor versions, I believe). */
#define TARGET_VERSION \
fprintf (stderr, " [FALCON%s]", FALCON_SUBTARGET_VERSION)
/* For the falcon-*-elf subtarget. */
#define FALCON_SUBTARGET_VERSION " - generic ELF"
#define OVERRIDE_OPTIONS falcon_override_options ()
#define OPTIMIZATION_OPTIONS(OPTIMIZE, SIZE) \
do \
{ \
if ((OPTIMIZE) >= 2 || (SIZE)) \
{ \
flag_omit_frame_pointer = 1; \
} \
} \
while (0)
/* Node: Storage Layout */
#define BITS_BIG_ENDIAN 0
#define BYTES_BIG_ENDIAN 0
#define WORDS_BIG_ENDIAN 0
#define UNITS_PER_WORD 4
/* A combination of defining PROMOTE_FUNCTION_MODE,
TARGET_PROMOTE_FUNCTION_ARGS that always returns true
and *not* defining TARGET_PROMOTE_PROTOTYPES or PROMOTE_MODE gives the
best code size and speed for gcc, ipps and products in gcc-2.7.2. */
#define FALCON_PROMOTED_MODE(MODE, UNSIGNEDP, TYPE) \
(GET_MODE_CLASS (MODE) == MODE_INT && GET_MODE_SIZE (MODE) < 4) \
? SImode : MODE
#define PROMOTE_FUNCTION_MODE(MODE, UNSIGNEDP, TYPE) \
(MODE) = FALCON_PROMOTED_MODE (MODE, UNSIGNEDP, TYPE)
#define PARM_BOUNDARY 32
#define STACK_BOUNDARY 32
#define FUNCTION_BOUNDARY 8
#define BIGGEST_ALIGNMENT 32
#define EMPTY_FIELD_BOUNDARY 8
#define STRUCTURE_SIZE_BOUNDARY 8
#define STRICT_ALIGNMENT 1
#define MAX_FIXED_MODE_SIZE 32
#undef PCC_BITFIELD_TYPE_MATTERS
/* Node: Type Layout */
/* Note that DOUBLE_TYPE_SIZE is not defined anymore, since the default
value gives a 64-bit double, which is what we now use. */
/* For compatibility and historical reasons, a char should be signed. */
#define DEFAULT_SIGNED_CHAR 1
/* Note that WCHAR_TYPE_SIZE is used in cexp.y,
where TARGET_SHORT is not available. */
#undef WCHAR_TYPE
#define WCHAR_TYPE "long int"
#undef WCHAR_TYPE_SIZE
#define WCHAR_TYPE_SIZE 32
/* Node: Register Basics */
/* We count:
- all 16 non-special registers
- SP (16) : stack pointer
- PC (17) : program counter
- AP (18) : a (faked) argument pointer register
*/
#define FIRST_PSEUDO_REGISTER (16 + 1 + 1 + 1)
/* For FALCON, register r8 is used as a frame-pointer, but is not fixed.
All other special registers are fixed, including the faked argument
pointer register */
#define FIXED_REGISTERS \
{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1}
/* Register r9 is used for structure-address, r10-r15 for parameters,
r10- for return values. */
#define CALL_USED_REGISTERS \
{0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1}
/* Node: Allocation Order */
/* We need this on FALCON, because call-used regs should be used first,
(so we don't need to push). Else start using registers from r0 and up.
This preference is mainly because if we put call-used-regs from r0
and up, then we can't use movem to push the rest, (which have to be
saved if we use them, and movem has to start with r0).
Change here if you change which registers to use as call registers.
The actual need to explicitly prefer call-used registers improved the
situation a lot for 2.1, but might not actually be needed anymore.
Still, this order reflects what GCC should find out by itself, so it
probably does not hurt.
Order of preference: Call-used-regs first, then r0 and up, last fp &
sp & pc as fillers.
Call-used regs in opposite order, so they will cause less conflict if
a function has few args (<= 5) and it wants a scratch reg.
Use struct-return address first, since very few functions use
structure return values so it is likely to be available. */
#define REG_ALLOC_ORDER \
{9, 15, 14, 13, 12, 11, 10, 0, 1, 2, 3, 4, 5, 6, 7, 8}
/* Node: Values in Registers */
/* The VOIDmode test is so we can omit mode on anonymous insns. FIXME:
Still needed in 2.9x, at least for Axis-20000319. */
#define HARD_REGNO_NREGS(REGNO, MODE) \
(MODE == VOIDmode \
? 1 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
/* FALCON permits all registers to hold all modes. Well, except for the
condition-code register. */
#define HARD_REGNO_MODE_OK(REGNO, MODE) \
(((MODE) == CCmode \
|| (REGNO) != FALCON_SP_REGNUM) \
)
/* Because CCmode isn't covered by the "narrower mode" statement in
tm.texi, we can still say all modes are tieable despite not having an
always 1 HARD_REGNO_MODE_OK. */
#define MODES_TIEABLE_P(MODE1, MODE2) 1
/* Node: Leaf Functions */
/* (no definitions) */
/* Node: Stack Registers */
/* (no definitions) */
/* Node: Register Classes */
enum reg_class
{
NO_REGS,
SP_REGS, SPECIAL_REGS, GENERAL_REGS, ALL_REGS,
LIM_REG_CLASSES
};
#define N_REG_CLASSES (int) LIM_REG_CLASSES
#define REG_CLASS_NAMES \
{"NO_REGS", "SP_REGS", "SPECIAL_REGS", "GENERAL_REGS", "ALL_REGS"}
#define FALCON_GENERAL_REGS_CONTENTS 0xffff
#define FALCON_SP_REGS_CONTENTS \
( (1 << FALCON_SP_REGNUM) )
#define FALCON_SPECIAL_REGS_CONTENTS \
( (1 << FALCON_SP_REGNUM) \
| (1 << FALCON_AP_REGNUM) \
| (1 << FALCON_PC_REGNUM) \
)
#define REG_CLASS_CONTENTS \
{ \
{0}, \
{FALCON_SP_REGS_CONTENTS}, \
{FALCON_SPECIAL_REGS_CONTENTS}, \
{FALCON_GENERAL_REGS_CONTENTS}, \
{FALCON_GENERAL_REGS_CONTENTS | FALCON_SPECIAL_REGS_CONTENTS} \
}
#define REGNO_REG_CLASS(REGNO) \
((REGNO) == FALCON_SP_REGNUM ? SP_REGS : \
(REGNO) == FALCON_AP_REGNUM ? SPECIAL_REGS : \
(REGNO) == FALCON_PC_REGNUM ? SPECIAL_REGS : \
GENERAL_REGS)
#define BASE_REG_CLASS GENERAL_REGS
#define INDEX_REG_CLASS GENERAL_REGS
#define REG_CLASS_FROM_LETTER(C) \
((C) == 'x' ? SP_REGS : \
NO_REGS \
)
/* All registers can serve as base registers. */
#define REGNO_OK_FOR_BASE_P(REGNO) (((REGNO) < FIRST_PSEUDO_REGISTER) \
||(unsigned) reg_renumber[REGNO] <
FIRST_PSEUDO_REGISTER)
#define REGNO_OK_FOR_BASE_P_NONSTRICT(REGNO) 1
/* See REGNO_OK_FOR_BASE_P. */
#define REGNO_OK_FOR_INDEX_P(REGNO) REGNO_OK_FOR_BASE_P(REGNO)
/* It seems like gcc (2.7.2 and 2.9x of 2000-03-22) may send "NO_REGS" as
the class for a constant (testcase: __Mul in arit.c). To avoid forcing
out a constant into the constant pool, we will trap this case and
return something a bit more sane. FIXME: Check if this is a bug.
Beware that we must not "override" classes that can be specified as
constraint letters, or else asm operands using them will fail when
they need to be reloaded. FIXME: Investigate whether that constitutes
a bug. */
#define PREFERRED_RELOAD_CLASS(X, CLASS) CLASS
/* We can't move special registers to and from memory in smaller than
word_mode. */
#define SECONDARY_RELOAD_CLASS(CLASS, MODE, X) \
((CLASS) != SPECIAL_REGS \
|| GET_MODE_SIZE (MODE) == 4 \
|| GET_CODE (X) != MEM \
? NO_REGS : GENERAL_REGS)
/* For FALCON, this is always the size of MODE in words,
since all registers are the same size. To use omitted modes in
patterns with reload constraints, you must say the widest size
which is allowed for VOIDmode.
FIXME: Does that still apply for gcc-2.9x? Keep poisoned until such
patterns are added back. News: 2001-03-16: Happens as early as the
underscore-test. */
#define CLASS_MAX_NREGS(CLASS, MODE) \
((MODE) == VOIDmode \
? 1 /* + falcon_fatal ("CLASS_MAX_NREGS with VOIDmode") */ \
: ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
/* Constant constraints. */
#define CONST_OK_FOR_LETTER_P(VALUE, C) \
( \
/* SImm(16). */ \
(C) == 'I' ? (VALUE) >= -0x8000 && (VALUE) <= 0x8000 : \
/* Imm(16) . */ \
(C) == 'J' ? (VALUE) >= 0 && (VALUE) < 0x10000 : \
/* -Imm(16) . */ \
(C) == 'K' ? (VALUE) < 0 && (VALUE) > -0x10000 : \
/* Zero. */ \
(C) == 'L' ? (VALUE) == 0 : \
0)
#define EXTRA_CONSTRAINT(X, C) \
( \
(C) == 'Q' ? ( CONSTANT_P(X) \
&& GET_CODE(X) != CONST_INT \
&& !TARGET_LARGE_CODE \
) : \
(C) == 'R' ? ( GET_CODE(X) == MEM \
&& falcon_non_indexed_p( \
XEXP(X,0), GET_MODE(X) \
)) : \
0)
#define EXTRA_MEMORY_CONSTRAINT(X, STR) ((X) == 'R')
/* We want the unary operators visible for constraint checking.
(will always be the case in 4.2). */
#define KEEP_UNARY_OPERATORS_AT_CONSTRAINT_CHECKING
/* Node: Frame Layout */
#define STACK_GROWS_DOWNWARD 1
#define FRAME_GROWS_DOWNWARD 1
/* It seems to be indicated in the code (at least 2.1) that this is
better a constant, and best 0. */
#define STARTING_FRAME_OFFSET 0
#define FIRST_PARM_OFFSET(FNDECL) 0
#define RETURN_ADDR_RTX(COUNT, FRAMEADDR) \
falcon_return_addr_rtx (COUNT, FRAMEADDR)
#define INCOMING_RETURN_ADDR_RTX \
gen_rtx_MEM (Pmode, plus_constant(stack_pointer_rtx, -4))
/* FIXME: Any __builtin_eh_return callers must not return anything and
there must not be collisions with incoming parameters. Luckily the
number of __builtin_eh_return callers is limited. For now return
parameter registers in reverse order and hope for the best. */
#define EH_RETURN_DATA_REGNO(N) \
(IN_RANGE ((N), 0, FALCON_MAX_ARGS_IN_REGSM1) ? (FALCON_FIRST_ARG_REG +
FALCON_MAX_ARGS_IN_REGSM1 - (N)) : INVALID_REGNUM)
/* Store the stack adjustment in the structure-return-address register. */
#define FALCON_STACKADJ_REG FALCON_STRUCT_VALUE_REGNUM
#define EH_RETURN_STACKADJ_RTX gen_rtx_REG (SImode, FALCON_STACKADJ_REG)
#define EH_RETURN_HANDLER_RTX \
falcon_return_addr_rtx (0, NULL)
#define INIT_EXPANDERS falcon_init_expanders ()
/* @@JVDS: It is not clear what we need here (it's not documented properly
yet). * /
#define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM(FALCON_SRP_REGNUM)
*/
/* FIXME: Move this to right node (it's not documented properly yet).
*/
#define DWARF_CIE_DATA_ALIGNMENT -1
/* If we would ever need an exact mapping between canonical register
number and dwarf frame register, we would either need to include all
registers in the gcc description (with some marked fixed of course), or
an inverse mapping from dwarf register to gcc register. There is one
need in dwarf2out.c:expand_builtin_init_dwarf_reg_sizes. Right now, I
don't see that we need exact correspondence between DWARF *frame*
registers and DBX_REGISTER_NUMBER, so map them onto GCC registers. */
#define DWARF_FRAME_REGNUM(REG) (REG)
/* Node: Stack Checking */
/* (no definitions) FIXME: Check. */
/* Node: Frame Registers */
#define STACK_POINTER_REGNUM FALCON_SP_REGNUM
#define FRAME_POINTER_REGNUM FALCON_FP_REGNUM
#define ARG_POINTER_REGNUM FALCON_AP_REGNUM
#define STATIC_CHAIN_REGNUM FALCON_STATIC_CHAIN_REGNUM
/* Node: Elimination */
/* Really only needed if the stack frame has variable length (alloca
or variable sized local arguments (GNU C extension). */
#define FRAME_POINTER_REQUIRED 0
#define ELIMINABLE_REGS \
{{ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
{ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM}, \
{FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}}
/* We need not worry about when the frame-pointer is required for other
reasons. */
#define CAN_ELIMINATE(FROM, TO) 1
#define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
(OFFSET) = falcon_initial_elimination_offset (FROM, TO)
/* Node: Stack Arguments */
/* Since many parameters take up one register each in any case,
defining TARGET_PROMOTE_PROTOTYPES that always returns true would
seem like a good idea, but measurements indicate that a combination
using PROMOTE_MODE is better. */
#define ACCUMULATE_OUTGOING_ARGS 1
#define RETURN_POPS_ARGS(FUNDECL, FUNTYPE, STACKSIZE) 0
/* Node: Register Arguments */
/* The void_type_node is sent as a "closing" call. */
#define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
((CUM).regs < FALCON_MAX_ARGS_IN_REGS \
? gen_rtx_REG (MODE, (FALCON_FIRST_ARG_REG) + (CUM).regs) \
: NULL_RTX)
/* The differences between this and the previous, is that this one checks
that an argument is named, since incoming stdarg/varargs arguments are
pushed onto the stack, and we don't have to check against the "closing"
void_type_node TYPE parameter. */
#define FUNCTION_INCOMING_ARG(CUM, MODE, TYPE, NAMED) \
((NAMED) && (CUM).regs < FALCON_MAX_ARGS_IN_REGS \
? gen_rtx_REG (MODE, FALCON_FIRST_ARG_REG + (CUM).regs) \
: NULL_RTX)
/* Contrary to what you'd believe, defining FUNCTION_ARG_CALLEE_COPIES
seems like a (small total) loss, at least for gcc-2.7.2 compiling and
running gcc-2.1 (small win in size, small loss running -- 100.1%),
and similarly for size for products (.1 .. .3% bloat, sometimes win).
Due to the empirical likeliness of making slower code, it is not
defined. */
/* This no longer *needs* to be a structure; but keeping it as such should
not hurt (and hacking the ABI is simpler). */
#define CUMULATIVE_ARGS struct cum_args
struct cum_args {int regs;};
/* The regs member is an integer, the number of arguments got into
registers so far. */
#define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \
((CUM).regs = 0)
#define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
((CUM).regs += (3 + FALCON_FUNCTION_ARG_SIZE (MODE, TYPE)) / 4)
#define FUNCTION_ARG_REGNO_P(REGNO) \
((REGNO) >= FALCON_FIRST_ARG_REG \
&& (REGNO) < FALCON_FIRST_ARG_REG + (FALCON_MAX_ARGS_IN_REGS))
/* Node: Scalar Return */
/* Let's assume all functions return in r[FALCON_FIRST_ARG_REG] for the
time being. */
#define FUNCTION_VALUE(VALTYPE, FUNC) \
gen_rtx_REG (TYPE_MODE (VALTYPE), FALCON_FIRST_ARG_REG)
#define LIBCALL_VALUE(MODE) gen_rtx_REG (MODE, FALCON_FIRST_ARG_REG)
#define FUNCTION_VALUE_REGNO_P(N) ((N) == FALCON_FIRST_ARG_REG)
/* Node: Aggregate Return */
#define FALCON_STRUCT_VALUE_REGNUM ((FALCON_FIRST_ARG_REG) - 1)
/* Node: Caller Saves */
/* (no definitions) */
/* Node: Function entry */
/* See falcon.c for TARGET_ASM_FUNCTION_PROLOGUE and
TARGET_ASM_FUNCTION_EPILOGUE. */
/* Node: Profiling */
#define FUNCTION_PROFILER(FILE, LABELNO) \
error ("no FUNCTION_PROFILER for FALCON")
/* FIXME: Some of the undefined macros might be mandatory. If so, fix
documentation. */
/* Node: Trampolines */
/* This looks too complicated, and it is. I assigned r7 to be the
static chain register, but it is call-saved, so we have to save it,
and come back to restore it after the call, so we have to save srp...
Anyway, trampolines are rare enough that we can cope with this
somewhat lack of elegance.
(Do not be tempted to "straighten up" whitespace in the asms; the
assembler #NO_APP state mandates strict spacing). */
#define TRAMPOLINE_TEMPLATE(FILE) \
do \
{ \
fprintf (FILE, "\t@@@@@TODO@@@@@@\n"); \
fprintf (FILE, "\tmove.d $%s,[$pc+20]\n", \
reg_names[STATIC_CHAIN_REGNUM]); \
fprintf (FILE, "\tmove $srp,[$pc+22]\n"); \
fprintf (FILE, "\tmove.d 0,$%s\n", \
reg_names[STATIC_CHAIN_REGNUM]); \
fprintf (FILE, "\tjsr 0\n"); \
fprintf (FILE, "\tmove.d 0,$%s\n", \
reg_names[STATIC_CHAIN_REGNUM]); \
fprintf (FILE, "\tjump 0\n"); \
fprintf (FILE, "\t@@@@@TODO@@@@@@\n"); \
} \
while (0)
#define TRAMPOLINE_SIZE 32
/* FALCON wants instructions on word-boundary.
Note that due to a bug (reported) in 2.7.2 and earlier, this is
actually treated as alignment in _bytes_, not _bits_. (Obviously
this is not fatal, only a slight waste of stack space). */
#define TRAMPOLINE_ALIGNMENT 32
#define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
do \
{ \
emit_move_insn (gen_rtx_MEM (SImode, \
plus_constant (TRAMP, 10)), \
CXT); \
emit_move_insn (gen_rtx_MEM (SImode, \
plus_constant (TRAMP, 16)), \
FNADDR); \
} \
while (0)
/* Note that there is no need to do anything with the cache for sake of
a trampoline. */
/* Node: Library Calls */
/* If you change this, you have to check whatever libraries and systems
that use it. */
#define TARGET_EDOM 33
/* Node: Addressing Modes */
#define HAVE_PRE_INCREMENT 0
#define HAVE_PRE_DECREMENT 0
#define HAVE_POST_DECREMENT 0
#define HAVE_POST_INCREMENT 0
#define HAVE_PRE_MODIFY_REG 0
#define HAVE_POST_MODIFY_REG 0
#define HAVE_PRE_MODIFY_DISP 0
#define HAVE_POST_MODIFY_DISP 0
#define CONSTANT_ADDRESS_P(X) 0
#define MAX_REGS_PER_ADDRESS 2
/* There are helper macros defined here which are used only in
GO_IF_LEGITIMATE_ADDRESS.
Note that you *have to* reject invalid addressing modes for mode
MODE, even if it is legal for normal addressing modes. You cannot
rely on the constraints to do this work. They can only be used to
doublecheck your intentions. */
#define FALCON_SWAP_RTX(x,y) \
{ rtx h=(x); (x)=(y); (y)=h; }
#define BASE_P(X) \
(REG_P (X) && REG_OK_FOR_BASE_P (X))
#define FALCON_IS_INT(X,i) \
( GET_CODE (X)==CONST_INT \
&& INTVAL(X)>=(i) )
#define FALCON_GO_IF_DISPLACEMENT(MODE,X,ADDR) \
if ( GET_CODE(X)==CONST_INT \
&& INTVAL(X)>=0 \
&& INTVAL(X)< (256 * GET_MODE_SIZE(MODE)) \
) goto ADDR;
#define FALCON_GO_IF_INDEX(MODE,X,ADDR) \
if ( GET_CODE(X)==MULT ) { \
rtx x1 = XEXP (X, 0); \
rtx x2 = XEXP (X, 1); \
if (BASE_P(x2)) { FALCON_SWAP_RTX(x1,x2); } \
if (BASE_P(x1) && FALCON_IS_INT( x2, GET_MODE_SIZE(MODE) )) goto ADDR; \
}
#define FALCON_GO_IF_DISPL_OR_INDEX(MODE,X,ADDR) \
{ FALCON_GO_IF_DISPLACEMENT(MODE,X,ADDR); \
FALCON_GO_IF_INDEX (MODE,X,ADDR); \
}
#define ___GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR, COND) \
{ \
if (BASE_P (X)) goto ADDR; \
\
if (GET_CODE (X) == PLUS) { \
rtx y1 = XEXP (X, 0); \
rtx y2 = XEXP (X, 1); \
if (BASE_P(y2)) { FALCON_SWAP_RTX(y1,y2); } \
if (BASE_P(y1)) { COND(MODE,y2,ADDR); } \
} else \
\
if ( GET_CODE (X) == POST_INC || GET_CODE (X) == PRE_DEC ) { \
rtx x1 = XEXP (X, 0); \
if ( REG_P(x1) && REGNO(x1)==FALCON_SP_REGNUM ) { \
goto ADDR; \
} \
} \
}
#define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
___GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR, FALCON_GO_IF_DISPL_OR_INDEX)
#ifndef REG_OK_STRICT
/* Nonzero if X is a hard reg that can be used as a base reg
or if it is a pseudo reg. */
# define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P_NONSTRICT (REGNO (X))
#else
/* Nonzero if X is a hard reg that can be used as a base reg. */
# define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X))
#endif
#ifndef REG_OK_STRICT
/* Nonzero if X is a hard reg that can be used as an index
or if it is a pseudo reg. */
# define REG_OK_FOR_INDEX_P(X) REG_OK_FOR_BASE_P (X)
#else
/* Nonzero if X is a hard reg that can be used as an index. */
# define REG_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X))
#endif
/*
* Except for stack pop and push (which are handled during
* the assembly emit phase), there are no address expressions
* on the Falcon with mode dependent semantics.
*/
#define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL)
#define LEGITIMATE_CONSTANT_P(X) 1
/* Node: Condition Code */
#define NOTICE_UPDATE_CC(EXP, INSN)
/* FIXME: Maybe define CANONICALIZE_COMPARISON later, when playing with
optimizations. It is needed; currently we do this with instruction
patterns and NOTICE_UPDATE_CC. */
/* Node: Costs */
/* Can't move to and from a SPECIAL_REGS register, so we have to say
their move cost within that class is higher. How about 7? That's 3
for a move to a GENERAL_REGS register, 3 for the move from the
GENERAL_REGS register, and 1 for the increased register pressure.
Also, it's higher than the memory move cost, which is in order.
We also do this for ALL_REGS, since we don't want that class to be
preferred (even to memory) at all where GENERAL_REGS doesn't fit.
Whenever it's about to be used, it's for SPECIAL_REGS. If we don't
present a higher cost for ALL_REGS than memory, a SPECIAL_REGS may be
used when a GENERAL_REGS should be used, even if there are call-saved
GENERAL_REGS left to allocate. This is because the fall-back when
the most preferred register class isn't available, isn't the next
(or next good) wider register class, but the *most widest* register
class.
Give the cost 3 between a special register and a general register,
because we want constraints verified. */
#define REGISTER_MOVE_COST(MODE, FROM, TO) \
(((FROM) == SPECIAL_REGS && (TO) == SPECIAL_REGS ) \
|| (FROM) == ALL_REGS \
|| (TO) == ALL_REGS \
? 7 : \
((FROM) == SPECIAL_REGS || (TO) == SPECIAL_REGS) \
? 3 : 2)
/* This isn't strictly correct for v0..3 in buswidth-8bit mode, but
should suffice. */
#define MEMORY_MOVE_COST(M, CLASS, IN) \
(((M) == QImode) ? 4 : ((M) == HImode) ? 4 : 6)
/* The default value of 1 for
BRANCH_COST is the best in the range (1, 2, 3), tested with gcc-2.7.2
with testcases ipps and gcc, giving smallest and fastest code. */
#define SLOW_BYTE_ACCESS 0
/* This is the threshold *below* which inline move sequences of
word-length sizes will be emitted. The "9" will translate to
(9 - 1) * 4 = 32 bytes maximum moved, but using 16 instructions
(8 instruction sequences) or less. */
#define MOVE_RATIO 9
/* Node: Sections */
#define TEXT_SECTION_ASM_OP "\t.text"
#define DATA_SECTION_ASM_OP "\t.data"
#define FORCE_EH_FRAME_INFO_IN_DATA_SECTION 0
#define JUMP_TABLES_IN_TEXT_SECTION 0
#define PIC_OFFSET_TABLE_REGNUM INVALID_REGNUM
/* Node: File Framework */
/* We don't want an .ident for gcc. To avoid that but still support
#ident, we override ASM_OUTPUT_IDENT and, since the gcc .ident is its
only use besides ASM_OUTPUT_IDENT, undef IDENT_ASM_OP from elfos.h. */
#undef IDENT_ASM_OP
#undef ASM_OUTPUT_IDENT
#define ASM_OUTPUT_IDENT(FILE, NAME) \
fprintf (FILE, "%s\"%s\"\n", "\t.ident\t", NAME);
#define ASM_APP_ON ""
#define ASM_APP_OFF ""
/* Node: Uninitialized Data */
/* Remember to round off odd values if we want data alignment,
since we cannot do that with an .align directive.
Using .comm causes the space not to be reserved in .bss, but by
tricks with the symbol type. Not good if other tools than binutils
are used on the object files. Since ".global ... .lcomm ..." works, we
use that. Use .._ALIGNED_COMMON, since gcc whines when we only have
..._COMMON, and we prefer to whine ourselves; BIGGEST_ALIGNMENT is not
the one to check. This done for a.out only. */
/* FIXME: I suspect a bug in gcc with alignment. Do not warn until
investigated; it mucks up the testsuite results. */
#define FALCON_ASM_OUTPUT_ALIGNED_DECL_COMMON(FILE, DECL, NAME, SIZE, ALIGN,
LOCAL) \
do \
{ \
int align_ = (ALIGN) / BITS_PER_UNIT; \
/* FIXME: Do we need this? */ \
if (align_ < 1) align_ = 1; \
\
{ \
if (LOCAL) \
{ \
fprintf ((FILE), "%s", LOCAL_ASM_OP); \
assemble_name ((FILE), (NAME)); \
fprintf ((FILE), "\n"); \
} \
fprintf ((FILE), "%s", COMMON_ASM_OP); \
assemble_name ((FILE), (NAME)); \
fprintf ((FILE), ",%u,%u\n", (int)(SIZE), align_); \
} \
} \
while (0)
#define ASM_OUTPUT_ALIGNED_DECL_COMMON(FILE, DECL, NAME, SIZE, ALIGN) \
FALCON_ASM_OUTPUT_ALIGNED_DECL_COMMON(FILE, DECL, NAME, SIZE, ALIGN, 0)
#undef ASM_OUTPUT_ALIGNED_DECL_LOCAL
#define ASM_OUTPUT_ALIGNED_DECL_LOCAL(FILE, DECL, NAME, SIZE, ALIGN) \
FALCON_ASM_OUTPUT_ALIGNED_DECL_COMMON(FILE, DECL, NAME, SIZE, ALIGN, 1)
/* FIXME: define ASM_OUTPUT_SHARED_COMMON and emit an error when it is
used with -melinux and a.out. */
/* Node: Label Output */
/* Globalizing directive for a label. */
#define GLOBAL_ASM_OP "\t.global "
#define SUPPORTS_WEAK 1
#define ASM_OUTPUT_SYMBOL_REF(STREAM, SYM) \
falcon_asm_output_symbol_ref (STREAM, SYM)
#define ASM_OUTPUT_LABEL_REF(STREAM, BUF) \
falcon_asm_output_label_ref (STREAM, BUF)
/* Remove any previous definition (elfos.h). */
#undef ASM_GENERATE_INTERNAL_LABEL
#define ASM_GENERATE_INTERNAL_LABEL(LABEL, PREFIX, NUM) \
sprintf (LABEL, "*%s%s%ld", LOCAL_LABEL_PREFIX, PREFIX, (long) NUM)
/* Node: Initialization */
/* (no definitions) */
/* Node: Macros for Initialization */
/* (no definitions) */
/* Node: Instruction Output */
#define REGISTER_NAMES \
{"a0", "a1", "a2", "a3", "a4", "a5", "a6", "a7", "a8", \
"a9", "a10", "a11", "a12", "a13", "a14", "a15", "SP", "PC", "faked_ap"}
#define PRINT_OPERAND(FILE, X, CODE) \
falcon_print_operand (FILE, X, CODE)
#define PRINT_OPERAND_PUNCT_VALID_P(CODE) \
((CODE) == '#' || (CODE) == '!' || (CODE) == ':' || (CODE) == '@')
#define PRINT_OPERAND_ADDRESS(FILE, ADDR) \
falcon_print_operand_address (FILE, ADDR)
#define LOCAL_LABEL_PREFIX ".L"
/* Remove any previous definition (elfos.h). */
/* We use -fno-leading-underscore to remove it, when necessary. */
#undef USER_LABEL_PREFIX
#define USER_LABEL_PREFIX "_"
#define ASM_OUTPUT_REG_PUSH(FILE, REGNO) \
fprintf (FILE, "\tpush %s;\n", reg_names[REGNO])
#define ASM_OUTPUT_REG_POP(FILE, REGNO) \
fprintf (FILE, "\tpop %s;\n", reg_names[REGNO])
/* Node: Dispatch Tables */
#define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \
asm_fprintf (FILE, "\t%s %LL%d\n", (TARGET_LARGE_CODE?".word":".half"), VALUE)
/* Defined to also emit an .align in elfos.h. We don't want that. */
#undef ASM_OUTPUT_CASE_LABEL
/* Node: Exception Region Output */
/* (no definitions) */
/* FIXME: Fill in with our own optimized layout. */
/* Node: Alignment Output */
#define ASM_OUTPUT_ALIGN(FILE, LOG) \
fprintf (FILE, "\t.align %d\n", 1<<(LOG))
/* Node: All Debuggers */
#define DBX_REGISTER_NUMBER(REGNO) (REGNO)
/* Node: DBX Options */
/* Is this correct? Check later. */
#define DBX_NO_XREFS
#define DBX_CONTIN_LENGTH 0
/* FIXME: Is this needed when we have 0 DBX_CONTIN_LENGTH? */
#define DBX_CONTIN_CHAR '?'
/* Node: DBX Hooks */
/* (no definitions) */
/* Node: File names and DBX */
/* (no definitions) */
/* Node: SDB and DWARF */
/* (no definitions) */
/* Node: Misc */
#define CASE_VECTOR_MODE SImode
#define CASE_VALUES_THRESHOLD 4
/* FIXME: Investigate CASE_VECTOR_SHORTEN_MODE to make sure HImode is not
used when broken-.word could possibly fail (plus testcase). */
#define FIXUNS_TRUNC_LIKE_FIX_TRUNC
/* This is the number of bytes that can be moved in one
reasonably fast instruction sequence. For FALCON, this is two
instructions: mem => reg, reg => mem. */
#define MOVE_MAX 4
/* Maybe SHIFT_COUNT_TRUNCATED is safe to define? FIXME: Check later. */
#define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
#define Pmode SImode
#define FUNCTION_MODE QImode
#define NO_IMPLICIT_EXTERN_C
/* The operands passed to the last cmpMM expander. */
enum cmp_type {
cmp_none,
cmp_compare
};
enum cmp_type cmp_kind;
char *cmp_mode;
extern GTY(()) rtx cmp_operands[2];
