> BTW, carry-out from shifts is very rarely used in compiled code.) Unless you've expanded SI shifts into a pair of HI shifts.
> Besides what DJ said about performance (both pros and cons > there), the problem is as I said with port complexity, because > of the way you have to handle condition codes in gcc. Unless you tell gcc that the condition codes are hard register? That's what m32c does; it has separate cmp/jmp and most opcodes set flags, so I just set an attribute that says which flags are set by each insn. Then, I can add a reorg pass to delete the cmps if the previous insn that set the flags happened to set them right. > Anyway, at least keep a way to add reg+reg and reg+integer, load and > store of memory and load of integer and address without condition > code effects and your port has a chance to avoid the related bloat. At least, move/load/store shouldn't touch flags.
