Hi,
After the changes regarding the FPSCR handling, some SH test cases
started to fail. This fixes it. Tested with
make -k check-gcc RUNTESTFLAGS="sh.exp --target_board=sh-sim
\{-m4/-ml,-m2/-ml}"
to verify that the test case passes again. Committed as r218707.
Cheers,
Oleg
gcc/testsuite/ChangeLog:
PR target/53513
* gcc.target/sh/attr-isr-nosave_low_regs.c: Fix matching of expected
register push/pop sequences.
* gcc.target/sh/attr-isr.c: Likewise.
* gcc.target/sh/attr-isr-trapa.c: Likewise.
* gcc.target/sh/pragma-isr-nosave_low_regs.c: Likewise.
* gcc.target/sh/pragma-isr-trapa.c: Likewise.
* gcc.target/sh/pragma-isr-trapa2.c: Likewise.
Index: gcc/testsuite/gcc.target/sh/attr-isr-nosave_low_regs.c
===================================================================
--- gcc/testsuite/gcc.target/sh/attr-isr-nosave_low_regs.c (revision 218705)
+++ gcc/testsuite/gcc.target/sh/attr-isr-nosave_low_regs.c (working copy)
@@ -1,15 +1,14 @@
/* A call will clobber all call-saved registers.
If #pragma nosave_low_regs is specified, do not save/restore r0..r7.
(On SH3* and SH4* r0..r7 are banked)
- One of these registers will also do fine to hold the function address.
- Call-saved registers r8..r13 also don't need to be restored. */
+ Call-saved registers r8..r13 also don't need to be restored.
+ To test that we look for register push insns such as 'mov.l r0,@-r15'. */
/* { dg-do compile { target { { "sh*-*-*" } && nonpic } } } */
/* { dg-skip-if "" { "sh*-*-*" } { "-m1*" "-m2*" "-m5*" } { "" } } */
/* { dg-options "-O" } */
/* { dg-final { scan-assembler-times "rte" 1 } } */
-/* { dg-final { scan-assembler-not "\[^f\]r\[0-9\]\[ \t\]*," } } */
-/* { dg-final { scan-assembler-not "\[^f\]r\[89\]" } } */
-/* { dg-final { scan-assembler-not "\[^f\]r1\[,0-3\]" } } */
+/* { dg-final { scan-assembler-not "mov.l\tr\[0-9\],@-r15" } } */
+/* { dg-final { scan-assembler-not "mov.l\tr1\[0-4\],@-r15" } } */
/* { dg-final { scan-assembler-times "macl" 2 } } */
extern void bar (void);
Index: gcc/testsuite/gcc.target/sh/pragma-isr-nosave_low_regs.c
===================================================================
--- gcc/testsuite/gcc.target/sh/pragma-isr-nosave_low_regs.c (revision 218705)
+++ gcc/testsuite/gcc.target/sh/pragma-isr-nosave_low_regs.c (working copy)
@@ -1,15 +1,14 @@
/* A call will clobber all call-saved registers.
If #pragma nosave_low_regs is specified, do not save/restore r0..r7.
(On SH3* and SH4* r0..r7 are banked)
- One of these registers will also do fine to hold the function address.
- Call-saved registers r8..r13 also don't need to be restored. */
+ Call-saved registers r8..r14 also don't need to be restored.
+ To test that we look for register push insns such as 'mov.l r0,@-r15'. */
/* { dg-do compile { target { { "sh*-*-*" } && nonpic } } } */
/* { dg-skip-if "" { "sh*-*-*" } { "-m1*" "-m2*" "-m5*" } { "" } } */
/* { dg-options "-O" } */
/* { dg-final { scan-assembler-times "rte" 1 } } */
-/* { dg-final { scan-assembler-not "\[^f\]r\[0-9\]\[ \t\]*," } } */
-/* { dg-final { scan-assembler-not "\[^f\]r\[89\]" } } */
-/* { dg-final { scan-assembler-not "\[^f\]r1\[,0-3\]" } } */
+/* { dg-final { scan-assembler-not "mov.l\tr\[0-9\],@-r15" } } */
+/* { dg-final { scan-assembler-not "mov.l\tr1\[0-4\],@-r15" } } */
/* { dg-final { scan-assembler-times "macl" 2 } } */
extern void foo (void);
Index: gcc/testsuite/gcc.target/sh/attr-isr.c
===================================================================
--- gcc/testsuite/gcc.target/sh/attr-isr.c (revision 218705)
+++ gcc/testsuite/gcc.target/sh/attr-isr.c (working copy)
@@ -1,6 +1,14 @@
+/* The call will clobber r0..r7, which will need not be saved/restored, but
+ not the call-saved registers r8..r14. Check this by counting the register
+ push insns. */
/* { dg-do compile { target { { { sh-*-* sh[1234ble]*-*-* } && { ! sh2a*-*-* } } && nonpic } } } */
/* { dg-skip-if "" { "sh*-*-*" } { "-m2a*" } { "" } } */
/* { dg-options "-O" } */
+/* { dg-final { scan-assembler-times "rte" 1} } */
+/* { dg-final { scan-assembler-times "mov.l\tr\[0-7\],@-r15" 8 } } */
+/* { dg-final { scan-assembler-not "mov.l\tr\[89\],@-r15" } } */
+/* { dg-final { scan-assembler-not "mov.l\tr1\[0-4\],@-r15" } } */
+
extern void foo ();
void
@@ -8,13 +16,3 @@
{
foo ();
}
-
-/* { dg-final { scan-assembler-times "rte" 1} } */
-/* The call will clobber r0..r7, which will need not be saved/restored.
- One of these registers will do fine to hold the function address,
- hence the all-saved registers r8..r13 don't need to be restored. */
-/* { dg-final { scan-assembler-times "r15\[+\],\[ \t\]*r\[0-9\]\[ \t\]*\n" 8 } } */
-/* { dg-final { scan-assembler-times "\[^f\]r\[0-9\]\[ \t\]*," 8 } } */
-/* { dg-final { scan-assembler-not "\[^f\]r1\[0-3\]" } } */
-/* { dg-final { scan-assembler-times "macl" 2} } */
-/* { dg-final { scan-assembler-not "rte.*\n.*r15\[+\],r\[0-7\]\n" } } */
Index: gcc/testsuite/gcc.target/sh/pragma-isr-trapa.c
===================================================================
--- gcc/testsuite/gcc.target/sh/pragma-isr-trapa.c (revision 218705)
+++ gcc/testsuite/gcc.target/sh/pragma-isr-trapa.c (working copy)
@@ -3,10 +3,8 @@
/* { dg-skip-if "" { "sh*-*-*" } { "-m5*" } { "" } } */
/* { dg-options "-O" } */
/* { dg-final { scan-assembler-times "rte" 1 } } */
-/* { dg-final { scan-assembler-not "r\[0-7\]\[ \t,\]\[^\n\]*r15" } } */
-/* { dg-final { scan-assembler-not "@r15\[^\n\]*r\[0-7\]\n" } } */
-/* { dg-final { scan-assembler-not "r\[8-9\]" } } */
-/* { dg-final { scan-assembler-not "r1\[,0-3\]" } } */
+/* { dg-final { scan-assembler-not "mov.l\tr\[0-9\],@-r15" } } */
+/* { dg-final { scan-assembler-not "mov.l\tr1\[0-4\],@-r15" } } */
/* { dg-final { scan-assembler-not "macl" } } */
extern void foo (void);
Index: gcc/testsuite/gcc.target/sh/pragma-isr-trapa2.c
===================================================================
--- gcc/testsuite/gcc.target/sh/pragma-isr-trapa2.c (revision 218705)
+++ gcc/testsuite/gcc.target/sh/pragma-isr-trapa2.c (working copy)
@@ -6,13 +6,12 @@
/* { dg-skip-if "" { "sh*-*-*" } { "-m1" "-m2" "-m3" "-m4al" "*nofpu" "-m4-340*" "-m4-400*" "-m4-500*" "-m5*" } { "" } } */
/* { dg-options "-O" } */
/* { dg-final { scan-assembler-times "rte" 1 } } */
-/* { dg-final { scan-assembler-times "r\[0-7\]\n" 3 } } */
-/* { dg-final { scan-assembler-not "r\[8-9\]" } } */
-/* { dg-final { scan-assembler-not "r1\[,0-3\]" } } */
+/* { dg-final { scan-assembler-not "mov.l\tr\[0-9\],@-r15" } } */
+/* { dg-final { scan-assembler-not "mov.l\tr1\[0-4\],@-r15" } } */
/* { dg-final { scan-assembler-not "macl" } } */
/* Expect that fpscr needs to be saved, loaded and restored. */
-/* { dg-final { scan-assembler-times "\[^_\]fpscr" 3 } } */
+/* { dg-final { scan-assembler-times "\[^_\]fpscr" 4 } } */
extern void foo (void);
Index: gcc/testsuite/gcc.target/sh/attr-isr-trapa.c
===================================================================
--- gcc/testsuite/gcc.target/sh/attr-isr-trapa.c (revision 218705)
+++ gcc/testsuite/gcc.target/sh/attr-isr-trapa.c (working copy)
@@ -3,10 +3,8 @@
/* { dg-skip-if "" { "sh*-*-*" } { "-m5*" } { "" } } */
/* { dg-options "-O" } */
/* { dg-final { scan-assembler-times "rte" 1 } } */
-/* { dg-final { scan-assembler-not "r\[0-7\]\[ \t,\]\[^\n\]*r15" } } */
-/* { dg-final { scan-assembler-not "@r15\[^\n\]*r\[0-7\]\n" } } */
-/* { dg-final { scan-assembler-not "r\[8-9\]" } } */
-/* { dg-final { scan-assembler-not "r1\[,0-3\]" } } */
+/* { dg-final { scan-assembler-not "mov.l\tr\[0-9\],@-r15" } } */
+/* { dg-final { scan-assembler-not "mov.l\tr1\[0-4\],@-r15" } } */
/* { dg-final { scan-assembler-not "macl" } } */
extern void foo (void);
Index: gcc/testsuite/ChangeLog
===================================================================
--- gcc/testsuite/ChangeLog (revision 218706)
+++ gcc/testsuite/ChangeLog (working copy)
@@ -1,5 +1,16 @@
2014-12-13 Oleg Endo <olege...@gcc.gnu.org>
+ PR target/53513
+ * gcc.target/sh/attr-isr-nosave_low_regs.c: Fix matching of expected
+ register push/pop sequences.
+ * gcc.target/sh/attr-isr.c: Likewise.
+ * gcc.target/sh/attr-isr-trapa.c: Likewise.
+ * gcc.target/sh/pragma-isr-nosave_low_regs.c: Likewise.
+ * gcc.target/sh/pragma-isr-trapa.c: Likewise.
+ * gcc.target/sh/pragma-isr-trapa2.c: Likewise.
+
+2014-12-13 Oleg Endo <olege...@gcc.gnu.org>
+
* gcc.target/sh/sp-switch.c: Match zero or more underscores in
alt_stack symbol.
