Hi Matthew,
> -----Original Message-----
> From: Matthew Fortune [mailto:matthew.fort...@imgtec.com]
> Sent: Thursday, November 06, 2014 12:11 PM
> To: Moore, Catherine; 'gcc-patches@gcc.gnu.org' (gcc-
> patc...@gcc.gnu.org); Eric Christopher (echri...@gmail.com)
> Cc: Richard Sandiford; Rich Fuhler; Rozycki, Maciej; Myers, Joseph
> Subject: RE: [PATCHv4][MIPS] Implement O32 ABI extensions (GCC)
>
> Sorry to follow myself up. I realised that the new configure options should be
> documented in install.texi. The only change from V3 is the doc/install.texi
> change.
>
> The MIPS64 tests have completed without regression.
>
> Regards,
> Matthew
>
> gcc/
> * common/config/mips/mips-common.c (mips_handle_option):
> Ensure
> that -mfp32, -mfp64 disable -mfpxx and -mfpxx disables -mfp64.
> * config.gcc (--with-fp-32): New option.
> (--with-odd-spreg-32): Likewise.
> * config.in (HAVE_AS_DOT_MODULE): New config define.
> * config/mips/mips-protos.h
> (mips_secondary_memory_needed): New prototype.
> (mips_hard_regno_caller_save_mode): Likewise.
> * config/mips/mips.c (mips_get_reg_raw_mode): New static
> prototype.
> (mips_get_arg_info): Assert that V2SFmode is only handled specially
> with TARGET_PAIRED_SINGLE_FLOAT.
> (mips_return_mode_in_fpr_p): Likewise.
> (mips16_call_stub_mode_suffix): Likewise.
> (mips_get_reg_raw_mode): New static function.
> (mips_return_fpr_pair): O32 return values span two registers.
> (mips16_build_call_stub): Likewise.
> (mips_function_value_regno_p): Support both FP return registers.
> (mips_output_64bit_xfer): Use mthc1 whenever
> TARGET_HAS_MXHC1. Add
> specific cases for TARGET_FPXX to move via memory.
> (mips_dwarf_register_span): For TARGET_FPXX pretend that modes
> larger
> than UNITS_PER_FPREG 'span' one register.
> (mips_dwarf_frame_reg_mode): New static function.
> (mips_file_start): Switch to using .module instead of .gnu_attribute.
> No longer support FP ABI 4 (-mips32r2 -mfp64), replace with FP ABI 6.
> Add FP ABI 5 (-mfpxx) and FP ABI 7 (-mfp64 -mno-odd-spreg).
> (mips_save_reg, mips_restore_reg): Always represent DFmode
> frame
> slots with two CFI directives even for O32 FP64.
> (mips_for_each_saved_gpr_and_fpr): Account for fixed_regs when
> saving/restoring callee-saved registers.
> (mips_hard_regno_mode_ok_p): Implement O32 FP64A extension.
> (mips_secondary_memory_needed): New function.
> (mips_option_override): ABI check for TARGET_FLOATXX. Disable
> odd-numbered single-precision registers when using
> TARGET_FLOATXX.
> Implement -modd-spreg and defaults.
> (mips_conditional_register_usage): Redefine O32 FP64 to match O32
> FP32
> callee-saved behaviour.
> (mips_hard_regno_caller_save_mode): Implement.
> (TARGET_GET_RAW_RESULT_MODE): Define target hook.
> (TARGET_GET_RAW_ARG_MODE): Define target hook.
> (TARGET_DWARF_FRAME_REG_MODE): Define target hook.
> * config/mips/mips.h (TARGET_FLOAT32): New macro.
> (TARGET_O32_FP64A_ABI): Likewise.
> (TARGET_CPU_CPP_BUILTINS): TARGET_FPXX is __mips_fpr==0.
> Add
> _MIPS_SPFPSET builtin define.
> (MIPS_FPXX_OPTION_SPEC): New macro.
> (OPTION_DEFAULT_SPECS): Pass through --with-fp-32=* to -mfp and
> --with-odd-spreg-32=* to -m[no-]odd-spreg.
> (ISA_HAS_ODD_SPREG): New macro.
> (ISA_HAS_MXHC1): True for anything other than -mfp32.
> (ASM_SPEC): Pass through mfpxx, mfp64, -mno-odd-spreg and -
> modd-spreg.
> (MIN_FPRS_PER_FMT): Redefine in terms of TARGET_ODD_SPREG.
> (HARD_REGNO_CALLER_SAVE_MODE): Define. Implement O32
> FPXX extension
> (HARD_REGNO_CALL_PART_CLOBBERED): Likewise.
> (SECONDARY_MEMORY_NEEDED): Likewise.
> (FUNCTION_ARG_REGNO_P): Update for O32 FPXX and FP64
> extensions.
> * config/mips/mips.md (define_attr enabled): Implement O32 FPXX
> and
> FP64A ABI extensions.
> (move_doubleword_fpr<mode>): Use ISA_HAS_MXHC1 instead of
> TARGET_FLOAT64.
> * config/mips/mips.opt (mfpxx): New target option.
> (modd-spreg): Likewise.
> * config/mips/mti-elf.h (DRIVER_SELF_SPECS): Infer FP ABI from
> arch.
> * config/mips/mti-linux.h (DRIVER_SELF_SPECS): Likewise and
> remove
> fp64 sysroot.
> * config/mips/t-mti-elf: Remove fp64 multilib.
> * config/mips/t-mti-linux: Likewise.
> * configure.ac: Detect .module support.
> * configure: Regenerate.
> * doc/invoke.texi: Document -mfpxx, -modd-spreg, -mno-odd-spreg
> option.
> * doc/install.texi (--with-fp-32, --with-odd-spreg-32): Document new
> options.
>
> gcc/testsuite/
> * gcc.target/mips/args-1.c: Handle __mips_fpr == 0.
> * gcc.target/mips/call-clobbered-1.c: New.
> * gcc.target/mips/call-clobbered-2.c: New.
> * gcc.target/mips/call-clobbered-3.c: New.
> * gcc.target/mips/call-clobbered-4.c: New.
> * gcc.target/mips/call-clobbered-5.c: New.
> * gcc.target/mips/call-saved-4.c: New.
> * gcc.target/mips/call-saved-5.c: New.
> * gcc.target/mips/call-saved-6.c: New.
> * gcc.target/mips/mips.exp: Support -mfpxx, -ffixed-f*,
> and -m[no-]odd-spreg. Use _MIPS_SPFPSET to determine default
> odd-spreg option. Account for -modd-spreg in minimum arch code.
> * gcc.target/mips/movdf-1.c: New.
> * gcc.target/mips/movdf-2.c: New.
> * gcc.target/mips/movdf-3.c: New.
> * gcc.target/mips/oddspreg-1.c: New.
> * gcc.target/mips/oddspreg-2.c: New.
> * gcc.target/mips/oddspreg-3.c: New.
> * gcc.target/mips/oddspreg-4.c: New.
> * gcc.target/mips/oddspreg-5.c: New.
> * gcc.target/mips/oddspreg-6.c: New.
>
> libgcc/
> * config/mips/mips16.S: Set .module when supported. Update O32
> FP64 calling convention and use for FPXX when possible. Add FPXX
> calling convention fallback case.
The patch looks good. Please fix up these couple of nits prior to committing.
Catherine
Index: gcc/doc/invoke.texi
===================================================================
--- gcc/doc/invoke.texi (revision 217363)
+++ gcc/doc/invoke.texi (working copy)
@@ -17865,6 +17883,15 @@ operations.
Assume that the floating-point coprocessor supports double-precision
operations. This is the default.
+@item -modd-spreg
+@itemx -mno-odd-spreg
+@opindex modd-spreg
+@opindex mno-odd-spreg
+Enable the use of odd-numbered single-precision floating-point registers
+for the o32 ABI. This is the default for processors that are known to
+known to support these registers. When using the o32 FPXX ABI,
+@code{-mno-odd-spreg} is set by default.
+
extra "known to" here.
@item -mabs=2008
@itemx -mabs=legacy
@opindex mabs=2008
Index: gcc/doc/install.texi
===================================================================
--- gcc/doc/install.texi (revision 217363)
+++ gcc/doc/install.texi (working copy)
@@ -1256,6 +1256,33 @@ ISA for floating-point arithmetics. You can selec
enables @option{-msse2} or @samp{avx} which enables @option{-mavx} by default.
This option is only supported on i386 and x86-64 targets.
+@item --with-fp-32=@var{mode}
+On MIPS targets, set the default value for the @option{-mfp} option when using
+the o32 ABI. The possibilities for @var{mode} are:
+@table @code
+@item 32
+Use the o32 FP32 ABI extension, as with the @option{-mfp32} command-line
+option.
+@item xx
+Use the o32 FPXX ABI extension, as with the @option{-mfpxx} command-line
+option.
+@item 64
+Use the o32 FP64 ABI extension, as with the @option{-mfp64} command-line
+option.
+@end table
+In the absence of this configuration option the default convention is to use
+the o32 FP32 ABI extension.
+
s/default convention/default/
+@item --with-odd-spreg-32
+On MIPS targets, set the @option{-modd-spreg} option by default when using
+the o32 ABI.
+
+@item --without-odd-spreg-32
+On MIPS targets, set the @option{-mno-odd-spreg} option by default when using
+the o32 ABI. This is normally used in conjunction with
+@option{--with-fp-32=64} in order to target the o32 FP64A ABI extension by
+default.
+
s/extension by default./extension./
@item --with-nan=@var{encoding}
On MIPS targets, set the default encoding convention to use for the
special not-a-number (NaN) IEEE 754 floating-point data. The
Index: gcc/config/mips/mips.c
===================================================================
--- gcc/config/mips/mips.c (revision 217363)
+++ gcc/config/mips/mips.c (working copy)
@@ -18824,6 +19000,21 @@ mips_expand_vec_minmax (rtx target, rtx op0, rtx o
emit_insn (gen_rtx_SET (VOIDmode, target, x));
}
+/* Implement HARD_REGNO_CALLER_SAVE_MODE. */
+
+machine_mode
+mips_hard_regno_caller_save_mode (unsigned int regno,
+ unsigned int nregs,
+ machine_mode mode)
+{
+ /* For performance, to avoid saving/restoring upper parts of a register,
+ we return MODE as save mode when MODE is not VOIDmode. */
s/performance, to/performance, /
+ if (mode == VOIDmode)
+ return choose_hard_reg_mode (regno, nregs, false);
+ else
+ return mode;
+}
/* Implement TARGET_CASE_VALUES_THRESHOLD. */
unsigned int
cmoore@build6-lucid-cs:~$
