Hi Richard, Please find attached the patch implementing load-load/store-store bonding supported by P5600.
In P5600, 2 consecutive loads/stores of same type which access contiguous
memory locations are bonded together by instruction issue unit to dispatch
single load/store instruction which accesses both locations. This allows 2X
improvement in memory intensive code. This optimization can be performed for
LH, SH, LW, SW, LWC, SWC, LDC, SDC instructions.
This patch adds peephole2 patterns to identify such loads/stores, and put them
in parallel, so that the scheduler will not split it - thereby guarantying h/w
level load/store bonding.
The patch is tested with dejagnu for correctness.
Local testing on hardware for perf is currently going on.
Ok for trunk?
Changelog:
gcc/
* config/mips/mips.md (JOINLDST1): New mode iterator.
(insn_type): New mode attribute.
(reg): Update mode attribute.
(join2_load_Store<JOINLDST1:mode>): New pattern.
(join2_loadhi): Likewise.
(join2_storehi): Likewise.
(define_peehole2): Add peephole2 patterns to join 2 HI/SI/SF/DF-mode
load-load and store-stores.
* config/mips/mips.opt (mld-st-pairing): New option.
* config/mips/mips.c (mips_option_override): New exception.
*config/mips/mips.h (ENABLE_LD_ST_PAIRING): New macro.
- Thanks and regards,
Sameera D.
load-store-pairing.patch
Description: load-store-pairing.patch
