Agree on checks:
/* PALIGNR of 2 128-bits registers takes only 1 instrucion.
Requires SSSE3. */
if (GET_MODE_SIZE (d->vmode) == 16)
{
if(!TARGET_SSSE3)
return false;
}
/* PALIGNR of 2 256-bits registers on AVX2 costs only 2 instructions:
PERM and PALIGNR. It is more profitable than 2 PSHUFB and PERM. */
else if (GET_MODE_SIZE (d->vmode) == 32)
{
if(!TARGET_AVX2)
return false;
}
else
return false;
On Mon, Apr 28, 2014 at 9:32 PM, Richard Henderson <[email protected]> wrote:
> On 04/28/2014 09:48 AM, Evgeny Stupachenko wrote:
>> - /* Even with AVX, palignr only operates on 128-bit vectors. */
>> - if (!TARGET_SSSE3 || GET_MODE_SIZE (d->vmode) != 16)
>> + /* PALIGNR of 2 256-bits registers on AVX2 costs only 2 instructions:
>> + PERM and PALIGNR. It is more profitable than 2 PSHUFB and PERM.
>> + PALIGNR of 2 128-bits registers takes only 1 instrucion. */
>> + if (!TARGET_SSSE3 || (GET_MODE_SIZE (d->vmode) != 16 &&
>> + GET_MODE_SIZE (d->vmode) != 32))
>> + return false;
>> + /* Only AVX2 or higher support PALIGNR on 256-bits registers. */
>> + if (!TARGET_AVX2 && (GET_MODE_SIZE (d->vmode) == 32))
>> return false;
>
> This is confusingly written.
>
> How about
>
> if (GET_MODE_SIZE (d->vmode) == 16)
> {
> if (!TARGET_SSSE3)
> return false;
> }
> else if (GET_MODE_SIZE (d->vmode) == 32)
> {
> if (!TARGET_AVX2)
> return false;
> }
> else
> return false;
>
> With the comments added into the right places.
>
>
> r~
