Hi Mike,
As discussed on irc, I'm applying the following as obvious to fix a
bug in the vsx fusion peepholes. The bug is simply that the peepholes
are enabled when -mno-vsx, which leads to replacing RTL that would
emit lvx insns with RTL that emits lxvw4x or lxvd2x. This is clearly
wrong, and worse, on LE causes permution of register words. I was
originally going to disable the peepholes entirely for little-endian
but on further thought decided this wasn't necessary: If TARGET_VSX
the original RTL insns these patterns match would emit vsx loads
anyway. If that changes in the future, ie. someone decides that vmx
loads are better on little-endian than vsx loads, then we'll need to
disable these peepholes for little-endian..
Bootstrapped and regression tested powerpc64-linux and
powerpc64le-linux. Fixes the following on powerpc64le-linux (where
power8 is now the default).
-FAIL: gcc.dg/vmx/3c-01.c -O2 -flto -fuse-linker-plugin -fno-fat-lto-objects
execution test
-FAIL: gcc.dg/vmx/varargs-4.c -O1 execution test
-FAIL: gcc.target/powerpc/ppc64-abi-2.c execution test
-FAIL: gfortran.fortran-torture/execute/constructor.f90 execution, -O2
-ftree-vectorize -maltivec
-FAIL: gfortran.fortran-torture/execute/elemental.f90 execution, -O2
-ftree-vectorize -maltivec
-FAIL: gfortran.fortran-torture/execute/forall_4.f90 execution, -O2
-ftree-vectorize -maltivec
-FAIL: gfortran.fortran-torture/execute/in-pack.f90 execution, -O2
-ftree-vectorize -maltivec
* config/rs6000/vsx.md (fusion peepholes): Disable when !TARGET_VSX.
Index: gcc/config/rs6000/vsx.md
===================================================================
--- gcc/config/rs6000/vsx.md (revision 205244)
+++ gcc/config/rs6000/vsx.md (working copy)
@@ -1895,7 +1895,7 @@
(set (match_operand:VSX_M2 2 "vsx_register_operand" "")
(mem:VSX_M2 (plus:P (match_dup 0)
(match_operand:P 3 "int_reg_operand" ""))))]
- "TARGET_P8_FUSION"
+ "TARGET_VSX && TARGET_P8_FUSION"
"li %0,%1\t\t\t# vector load fusion\;lx<VSX_M2:VSm>x %x2,%0,%3"
[(set_attr "length" "8")
(set_attr "type" "vecload")])
@@ -1906,7 +1906,7 @@
(set (match_operand:VSX_M2 2 "vsx_register_operand" "")
(mem:VSX_M2 (plus:P (match_operand:P 3 "int_reg_operand" "")
(match_dup 0))))]
- "TARGET_P8_FUSION"
+ "TARGET_VSX && TARGET_P8_FUSION"
"li %0,%1\t\t\t# vector load fusion\;lx<VSX_M2:VSm>x %x2,%0,%3"
[(set_attr "length" "8")
(set_attr "type" "vecload")])
--
Alan Modra
Australia Development Lab, IBM
