Uros,
We did not see any performance improvement on Atom in 32-bit mode at
routelookup from eembc_2_0 (eembc_1_1).
Best regards.
Yuri.
2012/12/13 Uros Bizjak <ubiz...@gmail.com>:
> On Thu, Dec 13, 2012 at 3:27 PM, Uros Bizjak <ubiz...@gmail.com> wrote:
>
>>> The patch proposed by Uros is useless since we don't have free scratch
>>> register to do splitting of memory operand:
>>>
>>> ;; regs ever live 0[ax] 1[dx] 2[cx] 3[bx] 4[si] 5[di] 6[bp] 7[sp]
>>> 17[flags]
>>>
>>> ...
>>>
>>> (insn 96 131 132 7 (set (reg/v/f:SI 6 bp [orig:70 trie_root ] [70])
>>> (if_then_else:SI (ne (reg:CCZ 17 flags)
>>> (const_int 0 [0]))
>>> (mem/f:SI (plus:SI (reg/v/f:SI 0 ax [orig:70 trie_root ] [70])
>>> (const_int 12 [0xc])) [2 trie_root_23->rlink+0 S4 A32])
>>> (reg/v/f:SI 6 bp [orig:70 trie_root ] [70])))
>>> routelookup/route_lookup.c:639 940 {*movsicc_noc}
>>> (expr_list:REG_DEAD (reg:CCZ 17 flags)
>>> (expr_list:REG_DEAD (reg/v/f:SI 0 ax [orig:70 trie_root ] [70])
>>> (nil))))
>>>
>>> How we can cope with this? I still assume that we can apply my patch
>>> with additional check on optimization for speed.
>>
>> Can you please post the testcase?
>
> Also, peephole2 pass recalculates life information by itself before
> every insn, so "regs ever live" array is not something to look at. The
> question was, if the patch solves the runtime regression for you, not
> if it removes all memory operands from the conditional moves. The
> split depends on optimize_insn_for_speed_p predicate.
>
> Uros.
