On 6/19/26 14:04, Aleksa Paunovic wrote:
> From: Chao-ying Fu <[email protected]>
>
> Ensure the proper sub-word address is computed
> when using built-in atomics on big-endian RISC-V targets.
>
> Without this change, multiple tests were failing, including:
> libatomic.c/atomic-compare-exchange-1.c
> libatomic.c/atomic-compare-exchange-2.c
> libatomic.c/atomic-exchange-1.c
> libatomic.c/atomic-exchange-2.c
> libatomic.c/atomic-op-1.c
> libatomic.c/atomic-op-2.c
> libatomic.c/generic-2.c
> gcc.target/riscv/amo/inline-atomics-3.c
> gcc.target/riscv/amo/inline-atomics-4.c
> gcc.target/riscv/amo/inline-atomics-5.c
> gcc.target/riscv/amo/inline-atomics-6.c
> gcc.target/riscv/amo/inline-atomics-7.c
> gcc.target/riscv/amo/inline-atomics-8.c
>
> The patch was tested using QEMU modified to run big-endian RISC-V
> executables [1].
>
> [1] https://github.com/djtodoro/qemu/tree/riscvbe/current#
>
> Signed-off-by: Aleksa Paunovic <[email protected]>
>
> gcc/ChangeLog:
>
> * config/riscv/riscv.cc (riscv_subword_address): Add emit_move_insn
> for big-endian.
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/riscv/amo/big-endian-subword-amo-hi.c: New test.
> * gcc.target/riscv/amo/big-endian-subword-amo-qi.c: New test.
> ---
> Changes in v4:
> - Drop the second and the third patches.
> - XFAIL the tests if RVV is enabled on big-endian builds instead of skipping.
> - Compile the tests with -O0 to avoid potential DCE issues.
> - Link to v3:
> https://patchwork.sourceware.org/project/gcc/cover/[email protected]/
>
> ---
> gcc/config/riscv/riscv.cc | 5 +++++
> .../gcc.target/riscv/amo/big-endian-subword-amo-hi.c | 10 ++++++++++
> .../gcc.target/riscv/amo/big-endian-subword-amo-qi.c | 10 ++++++++++
> 3 files changed, 25 insertions(+)
> create mode 100644
> gcc/testsuite/gcc.target/riscv/amo/big-endian-subword-amo-hi.c
> create mode 100644
> gcc/testsuite/gcc.target/riscv/amo/big-endian-subword-amo-qi.c
>
> diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
> index bd0046ad2e8..f0a6e43a182 100644
> --- a/gcc/config/riscv/riscv.cc
> +++ b/gcc/config/riscv/riscv.cc
> @@ -11969,6 +11969,11 @@ riscv_subword_address (rtx mem, rtx *aligned_mem,
> rtx *shift, rtx *mask,
> /* Calculate the shift amount. */
> emit_move_insn (*shift, gen_rtx_AND (SImode, gen_lowpart (SImode, addr),
> gen_int_mode (3, SImode)));
> + if (TARGET_BIG_ENDIAN)
> + emit_move_insn (*shift, gen_rtx_XOR (SImode, *shift,
> + gen_int_mode (GET_MODE (mem) == QImode
> + ? 3 : 2, SImode)));
> +
> emit_move_insn (*shift, gen_rtx_ASHIFT (SImode, *shift,
> gen_int_mode (3, SImode)));
>
> diff --git a/gcc/testsuite/gcc.target/riscv/amo/big-endian-subword-amo-hi.c
> b/gcc/testsuite/gcc.target/riscv/amo/big-endian-subword-amo-hi.c
> new file mode 100644
> index 00000000000..41e96dd583e
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/amo/big-endian-subword-amo-hi.c
> @@ -0,0 +1,10 @@
> +/* { dg-do compile } */
> +/* { dg-options "-mbig-endian -O0" } */
> +/* { dg-xfail-if "RVV is currently broken on big-endian RISC-V builds" {
> riscv*-*-* } { "-march=rv*v*" } } */
> +/* Verify that subword atomic operations use XOR for big-endian halfword
> alignment. */
> +/* { dg-final { scan-assembler "xori\\s+\[a-z0-9\]+,\[a-z0-9\]+,2" } } */
> +
> +void atomic_fetch_add_hi(short *ptr, short val)
> +{
> + __atomic_fetch_add(ptr, val, __ATOMIC_RELAXED);
> +}
> diff --git a/gcc/testsuite/gcc.target/riscv/amo/big-endian-subword-amo-qi.c
> b/gcc/testsuite/gcc.target/riscv/amo/big-endian-subword-amo-qi.c
> new file mode 100644
> index 00000000000..4e801140f96
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/amo/big-endian-subword-amo-qi.c
> @@ -0,0 +1,10 @@
> +/* { dg-do compile } */
> +/* { dg-options "-mbig-endian -O0" } */
> +/* { dg-xfail-if "RVV is currently broken on big-endian RISC-V builds" {
> riscv*-*-* } { "-march=rv*v*" } } */
> +/* Verify that subword atomic operations use XOR for big-endian byte
> alignment. */
> +/* { dg-final { scan-assembler "xori\\s+\[a-z0-9\]+,\[a-z0-9\]+,3" } } */
> +
> +void atomic_fetch_add_qi(char *ptr, char val)
> +{
> + __atomic_fetch_add(ptr, val, __ATOMIC_RELAXED);
> +}
Gentle ping.
