From: Pan Li <[email protected]> This patch would like to try to match the the unsigned SAT_MUL form 14.
The below test suites are passed for this patch: 1. The rv64gcv fully regression tests. 2. The x86 bootstrap tests. 3. The x86 fully regression tests. Pan Li (3): Match: Support unsigned scalar SAT_MUL form 14 RISC-V: Add testcase for unsigned scalar SAT_MUL form 14 RISC-V: Add testcase for unsigned scalar SAT_MUL form 15 gcc/match-sat-alu.pd | 24 ++++++++++++++ .../gcc.target/riscv/sat/sat_arith.h | 32 +++++++++++++++++++ .../riscv/sat/sat_u_mul-15-u16-from-u128.c | 11 +++++++ .../riscv/sat/sat_u_mul-15-u16-from-u32.c | 11 +++++++ .../sat/sat_u_mul-15-u16-from-u64.rv32.c | 11 +++++++ .../sat/sat_u_mul-15-u16-from-u64.rv64.c | 11 +++++++ .../riscv/sat/sat_u_mul-15-u32-from-u128.c | 11 +++++++ .../sat/sat_u_mul-15-u32-from-u64.rv32.c | 11 +++++++ .../sat/sat_u_mul-15-u32-from-u64.rv64.c | 11 +++++++ .../riscv/sat/sat_u_mul-15-u64-from-u128.c | 11 +++++++ .../riscv/sat/sat_u_mul-15-u8-from-u128.c | 11 +++++++ .../riscv/sat/sat_u_mul-15-u8-from-u16.c | 11 +++++++ .../riscv/sat/sat_u_mul-15-u8-from-u32.c | 11 +++++++ .../riscv/sat/sat_u_mul-15-u8-from-u64.rv32.c | 11 +++++++ .../riscv/sat/sat_u_mul-15-u8-from-u64.rv64.c | 11 +++++++ .../riscv/sat/sat_u_mul-16-u16-from-u128.c | 11 +++++++ .../riscv/sat/sat_u_mul-16-u16-from-u32.c | 11 +++++++ .../sat/sat_u_mul-16-u16-from-u64.rv32.c | 11 +++++++ .../sat/sat_u_mul-16-u16-from-u64.rv64.c | 11 +++++++ .../riscv/sat/sat_u_mul-16-u32-from-u128.c | 11 +++++++ .../sat/sat_u_mul-16-u32-from-u64.rv32.c | 11 +++++++ .../sat/sat_u_mul-16-u32-from-u64.rv64.c | 11 +++++++ .../riscv/sat/sat_u_mul-16-u64-from-u128.c | 11 +++++++ .../riscv/sat/sat_u_mul-16-u8-from-u128.c | 11 +++++++ .../riscv/sat/sat_u_mul-16-u8-from-u16.c | 11 +++++++ .../riscv/sat/sat_u_mul-16-u8-from-u32.c | 11 +++++++ .../riscv/sat/sat_u_mul-16-u8-from-u64.rv32.c | 11 +++++++ .../riscv/sat/sat_u_mul-16-u8-from-u64.rv64.c | 11 +++++++ .../sat/sat_u_mul-run-15-u16-from-u128.c | 16 ++++++++++ .../riscv/sat/sat_u_mul-run-15-u16-from-u32.c | 16 ++++++++++ .../riscv/sat/sat_u_mul-run-15-u16-from-u64.c | 16 ++++++++++ .../sat/sat_u_mul-run-15-u32-from-u128.c | 16 ++++++++++ .../riscv/sat/sat_u_mul-run-15-u32-from-u64.c | 16 ++++++++++ .../sat/sat_u_mul-run-15-u64-from-u128.c | 16 ++++++++++ .../riscv/sat/sat_u_mul-run-15-u8-from-u128.c | 16 ++++++++++ .../riscv/sat/sat_u_mul-run-15-u8-from-u16.c | 16 ++++++++++ .../riscv/sat/sat_u_mul-run-15-u8-from-u32.c | 16 ++++++++++ .../riscv/sat/sat_u_mul-run-15-u8-from-u64.c | 16 ++++++++++ .../sat/sat_u_mul-run-16-u16-from-u128.c | 16 ++++++++++ .../riscv/sat/sat_u_mul-run-16-u16-from-u32.c | 16 ++++++++++ .../riscv/sat/sat_u_mul-run-16-u16-from-u64.c | 16 ++++++++++ .../sat/sat_u_mul-run-16-u32-from-u128.c | 16 ++++++++++ .../riscv/sat/sat_u_mul-run-16-u32-from-u64.c | 16 ++++++++++ .../sat/sat_u_mul-run-16-u64-from-u128.c | 16 ++++++++++ .../riscv/sat/sat_u_mul-run-16-u8-from-u128.c | 16 ++++++++++ .../riscv/sat/sat_u_mul-run-16-u8-from-u16.c | 16 ++++++++++ .../riscv/sat/sat_u_mul-run-16-u8-from-u32.c | 16 ++++++++++ .../riscv/sat/sat_u_mul-run-16-u8-from-u64.c | 16 ++++++++++ 48 files changed, 662 insertions(+) create mode 100644 gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-15-u16-from-u128.c create mode 100644 gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-15-u16-from-u32.c create mode 100644 gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-15-u16-from-u64.rv32.c create mode 100644 gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-15-u16-from-u64.rv64.c create mode 100644 gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-15-u32-from-u128.c create mode 100644 gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-15-u32-from-u64.rv32.c create mode 100644 gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-15-u32-from-u64.rv64.c create mode 100644 gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-15-u64-from-u128.c create mode 100644 gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-15-u8-from-u128.c create mode 100644 gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-15-u8-from-u16.c create mode 100644 gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-15-u8-from-u32.c create mode 100644 gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-15-u8-from-u64.rv32.c create mode 100644 gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-15-u8-from-u64.rv64.c create mode 100644 gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-16-u16-from-u128.c create mode 100644 gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-16-u16-from-u32.c create mode 100644 gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-16-u16-from-u64.rv32.c create mode 100644 gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-16-u16-from-u64.rv64.c create mode 100644 gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-16-u32-from-u128.c create mode 100644 gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-16-u32-from-u64.rv32.c create mode 100644 gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-16-u32-from-u64.rv64.c create mode 100644 gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-16-u64-from-u128.c create mode 100644 gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-16-u8-from-u128.c create mode 100644 gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-16-u8-from-u16.c create mode 100644 gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-16-u8-from-u32.c create mode 100644 gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-16-u8-from-u64.rv32.c create mode 100644 gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-16-u8-from-u64.rv64.c create mode 100644 gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-15-u16-from-u128.c create mode 100644 gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-15-u16-from-u32.c create mode 100644 gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-15-u16-from-u64.c create mode 100644 gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-15-u32-from-u128.c create mode 100644 gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-15-u32-from-u64.c create mode 100644 gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-15-u64-from-u128.c create mode 100644 gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-15-u8-from-u128.c create mode 100644 gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-15-u8-from-u16.c create mode 100644 gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-15-u8-from-u32.c create mode 100644 gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-15-u8-from-u64.c create mode 100644 gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-16-u16-from-u128.c create mode 100644 gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-16-u16-from-u32.c create mode 100644 gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-16-u16-from-u64.c create mode 100644 gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-16-u32-from-u128.c create mode 100644 gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-16-u32-from-u64.c create mode 100644 gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-16-u64-from-u128.c create mode 100644 gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-16-u8-from-u128.c create mode 100644 gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-16-u8-from-u16.c create mode 100644 gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-16-u8-from-u32.c create mode 100644 gcc/testsuite/gcc.target/riscv/sat/sat_u_mul-run-16-u8-from-u64.c -- 2.43.0
