On Thu, Mar 26, 2026 at 03:43:02AM -0500, Vijay Shankar wrote:
> Hello,
>
> Changes form v1:
> * Cleaned up naming in rs6000.md
> * Cleaned up guards to be on same line.
> * Test case use \m...\M instead of relying on space
>
> Thank you,
> Vijay.
>
> POWER10 has instruction fusion for addis+addi pairs. However,
> the scheduler was breaking these pairs apart to optimize for
> dependency chains, losing the fusion benefit.
>
> This patch implements "fake" instructions that represent both
> instructions as a single pattern. This prevents the scheduler from
> reordering them while still generating the correct two-instruction
> sequence.
>
> Existing high/low patterns are guarded with !TARGET_POWER10 to
> prevent conflicts with the new fusion patterns.
I have a few issues with this patch.
This first is have you tested the patch on AIX? If not, we may want to
not do the AIX changes, particularly at this stage of the GCC 16
development. Now, in theory, it would help AIX users since I believe
they do not used prefixed addressing and the merge would be a possible
benefit on power10 due to fusion.
However, even without the AIX changes, I do't think it that helpful
under Linux systems because in order to get the patch to optimize user
code, the user much not use pc-relative addressing. Pc-relative
addressing is on by default when you use -mcpu=power10 or
-mcpu=power11. Sure, if the user uses -mno-pcrel or -mno-prefixed,
then this patch would match.
One case that it might work is if the user does either:
-mcpu=power9 -mtune=power10
-mcpu=power8 -mtune=power10
Then if we modify the patch to check if the code is tuned towards
power10, but not generating power10 code, we would want the addis to be
adjacent to the addi.
Lets talk about this later when GCC 17 opens up.
--
Michael Meissner, IBM
PO Box 98, Ayer, Massachusetts, USA, 01432
email: [email protected]
