On 3/29/26 4:35 PM, Vineet Gupta wrote:
On 3/29/26 4:17 PM, Vineet Gupta wrote:
From: Vineet Gupta <[email protected]>
movsi currently only generates DImode rN regs, despite RTL being SImode.
| (insn 14 5 11 (set (reg:SI 1 %r1 [23])
| (reg:SI 0 %r0)) {*movsi}
| (expr_list:REG_DEAD (reg:SI 0 %r0)
| (nil)))
generates
| r1 = r0
as opposed to
| w1 = w0
This is not just issue of taste or getting more wN regs. As
illustrated by test, this can be a correctness issue where mov
needs to zero out the upper bits.
Again the issue is asm teplmate of pattern missing 'w' specifier,
leading bpf_print_register() to only generate 64-bit rN regs.
Using 'w' allows either wN/rN reg depending on the mode.
PR target/124688
gcc/ChangeLog:
* config/bpf/bpf.md (*movsi): Add 'w' to asm template.
gcc/testsuite/ChangeLog:
* gcc.target/bpf/ret-reuse-arg-1.c: New test.
Signed-off-by: Vineet Gupta <[email protected]>
Oh just realized that this needs assembler update. So need to post
that first and also gate this change based on configure time detection
of updated gas.
Essentially gcc would now generate following 'w' + 'r' reg variants in
addition to the existing 'r' only form.
wN = *(u32 *)(rM + imm)
*(u32 *) (rM + imm) = wN
Added support to gas, however when asking Claude to generate gas
updates, it reports the encodins for both forms to be same. Further
disassembler will only generate the 'r' output. So to avoid confusion,
it would make sense for gcc mem alternate to not emit the 'w' form
despite SImode.
Thx,
-Vineet
