[PATCH 6/9][rs6000]: convert widen_[us]sum into convert optab [PR122069]

[Tamar Christina]

This patch is a mechanical rewrite of the widen_[us]sum optabs from a direct to
a conversion optab.  The result of which requires the output mode to be added to
the existing patterns.

No change in functionality is expected.

Ok for master?

Thanks,
Tamar

gcc/ChangeLog:

        PR middle-end/122069
        * config/rs6000/altivec.md (widen_usum<mode>3): Renamed ...
        (widen_usumv4si<mode>3): ... into this.
        (widen_ssumv16qi3): Renamed ...
        (widen_ssumv4siv16qi3): ... into this.
        (widen_ssumv8hi3): Renamed ...
        (widen_ssumv4siv8hi3): ... into this.

---
diff --git a/gcc/config/rs6000/altivec.md b/gcc/config/rs6000/altivec.md
index 
7edc288a65658c608a361caaa29a9f3fc2907b79..fa3368079ada661f3f159e27a3cf793698df1760
 100644
--- a/gcc/config/rs6000/altivec.md
+++ b/gcc/config/rs6000/altivec.md
@@ -3772,7 +3772,7 @@ (define_expand "sdot_prodv4siv8hi"
   DONE;
 })
 
-(define_expand "widen_usum<mode>3"
+(define_expand "widen_usumv4si<mode>3"
   [(set (match_operand:V4SI 0 "register_operand" "=v")
         (plus:V4SI (match_operand:V4SI 2 "register_operand" "v")
                    (unspec:V4SI [(match_operand:VIshort 1 "register_operand" 
"v")]
@@ -3786,7 +3786,7 @@ (define_expand "widen_usum<mode>3"
   DONE;
 })
 
-(define_expand "widen_ssumv16qi3"
+(define_expand "widen_ssumv4siv16qi3"
   [(set (match_operand:V4SI 0 "register_operand" "=v")
         (plus:V4SI (match_operand:V4SI 2 "register_operand" "v")
                    (unspec:V4SI [(match_operand:V16QI 1 "register_operand" 
"v")]
@@ -3800,7 +3800,7 @@ (define_expand "widen_ssumv16qi3"
   DONE;
 })
 
-(define_expand "widen_ssumv8hi3"
+(define_expand "widen_ssumv4siv8hi3"
   [(set (match_operand:V4SI 0 "register_operand" "=v")
         (plus:V4SI (match_operand:V4SI 2 "register_operand" "v")
                    (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")]


-- 

diff --git a/gcc/config/rs6000/altivec.md b/gcc/config/rs6000/altivec.md
index 7edc288a65658c608a361caaa29a9f3fc2907b79..fa3368079ada661f3f159e27a3cf793698df1760 100644
--- a/gcc/config/rs6000/altivec.md
+++ b/gcc/config/rs6000/altivec.md
@@ -3772,7 +3772,7 @@ (define_expand "sdot_prodv4siv8hi"
   DONE;
 })
 
-(define_expand "widen_usum<mode>3"
+(define_expand "widen_usumv4si<mode>3"
   [(set (match_operand:V4SI 0 "register_operand" "=v")
         (plus:V4SI (match_operand:V4SI 2 "register_operand" "v")
                    (unspec:V4SI [(match_operand:VIshort 1 "register_operand" "v")]
@@ -3786,7 +3786,7 @@ (define_expand "widen_usum<mode>3"
   DONE;
 })
 
-(define_expand "widen_ssumv16qi3"
+(define_expand "widen_ssumv4siv16qi3"
   [(set (match_operand:V4SI 0 "register_operand" "=v")
         (plus:V4SI (match_operand:V4SI 2 "register_operand" "v")
                    (unspec:V4SI [(match_operand:V16QI 1 "register_operand" "v")]
@@ -3800,7 +3800,7 @@ (define_expand "widen_ssumv16qi3"
   DONE;
 })
 
-(define_expand "widen_ssumv8hi3"
+(define_expand "widen_ssumv4siv8hi3"
   [(set (match_operand:V4SI 0 "register_operand" "=v")
         (plus:V4SI (match_operand:V4SI 2 "register_operand" "v")
                    (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")]