Hi Robin,
> diff --git a/gcc/config/riscv/tt-ascalon-d8.md
b/gcc/config/riscv/tt-ascalon-d8.md
> index a57c0b31a81..25b99b6129e 100644
> --- a/gcc/config/riscv/tt-ascalon-d8.md
> +++ b/gcc/config/riscv/tt-ascalon-d8.md
> @@ -285,38 +285,38 @@ (define_insn_reservation
"tt_ascalon_d8_vec_ordered_reduction" 10
> (define_insn_reservation "tt_ascalon_d8_vec_idiv_half" 16
> (and (eq_attr "tune" "tt_ascalon_d8")
> (eq_attr "type" "vidiv")
> - (eq_attr "mode" "HF"))
> + (eq_attr "sew" "16"))
> "tt_ascalon_d8_decode,(tt_ascalon_d8_vec0*3 | tt_ascalon_d8_vec1*3)")
>
> (define_insn_reservation "tt_ascalon_d8_vec_idiv_single" 13
> (and (eq_attr "tune" "tt_ascalon_d8")
> (eq_attr "type" "vidiv")
> - (eq_attr "mode" "SF"))
> + (eq_attr "sew" "32"))
> "tt_ascalon_d8_decode,(tt_ascalon_d8_vec0*3 | tt_ascalon_d8_vec1*3)")
I suppose SF and HF were typos in the first place, seeing they refer to integer
division?
Yeah, sorry that was my fault. Thanks Peter for fixing it.
No worries, I just wanted to make sure. These things easily slip through, in
particular when something is not compiled but just triggered at runtime.
--
Regards
Robin
