PR121878 shows a typo in the tt-ascalon-d8's pipeline description that
leads to an ICE. The problem is that the vector define_insn_reservation
patterns test for scalar modes rather than vector modes, meaning the
insns don't get handled correctly. We could correct the modes, but given
we could have multiple VLEN values, the number of modes we'd have to check
can be large and mode iterators are not allowed in the mode attribute check.
Instead, I've removed the mode check and replaced it with a test of the
Selected Elenent Width (SEW).
This patch fixes the ICE. Bootstrap and regtesting are in progress.
On today's RISC-V GCC patch review call, someone mentioned there might be an
alternative that uses a hook instead. Jeff mentioned this type of check
may be needed in other pipeline descriptions either now or in the future,
so I thought I'd post what I have so we can discuss which form is preferred.
Thought's on this solution versus the hook solution???
Peter
gcc/
PR target/121878
* config/riscv/tt-ascalon-d8.md (tt_ascalon_d8_vec_idiv_half): Test the
Selected Element Width (SEW) rather than the mode.
(tt_ascalon_d8_vec_idiv_single): Likewise.
(tt_ascalon_d8_vec_idiv_double): Likewise.
(tt_ascalon_d8_vec_float_divsqrt_half): Likewise.
(tt_ascalon_d8_vec_float_divsqrt_single): Likewise.
(tt_ascalon_d8_vec_float_divsqrt_double): Likewise.
gcc/testsuite/
PR target/121878
* gcc.target/riscv/pr121878.c: New test.
Signed-off-by: Peter Bergner <berg...@tenstorrent.com>
diff --git a/gcc/config/riscv/tt-ascalon-d8.md
b/gcc/config/riscv/tt-ascalon-d8.md
index a57c0b31a81..25b99b6129e 100644
--- a/gcc/config/riscv/tt-ascalon-d8.md
+++ b/gcc/config/riscv/tt-ascalon-d8.md
@@ -285,38 +285,38 @@ (define_insn_reservation
"tt_ascalon_d8_vec_ordered_reduction" 10
(define_insn_reservation "tt_ascalon_d8_vec_idiv_half" 16
(and (eq_attr "tune" "tt_ascalon_d8")
(eq_attr "type" "vidiv")
- (eq_attr "mode" "HF"))
+ (eq_attr "sew" "16"))
"tt_ascalon_d8_decode,(tt_ascalon_d8_vec0*3 | tt_ascalon_d8_vec1*3)")
(define_insn_reservation "tt_ascalon_d8_vec_idiv_single" 13
(and (eq_attr "tune" "tt_ascalon_d8")
(eq_attr "type" "vidiv")
- (eq_attr "mode" "SF"))
+ (eq_attr "sew" "32"))
"tt_ascalon_d8_decode,(tt_ascalon_d8_vec0*3 | tt_ascalon_d8_vec1*3)")
(define_insn_reservation "tt_ascalon_d8_vec_idiv_double" 20
(and (eq_attr "tune" "tt_ascalon_d8")
(eq_attr "type" "vidiv")
- (eq_attr "mode" "DF"))
+ (eq_attr "sew" "64"))
"tt_ascalon_d8_decode,(tt_ascalon_d8_vec0*3 | tt_ascalon_d8_vec1*3)")
;; Vector float divisions and sqrt
(define_insn_reservation "tt_ascalon_d8_vec_float_divsqrt_half" 11
(and (eq_attr "tune" "tt_ascalon_d8")
(eq_attr "type" "vfdiv,vfsqrt")
- (eq_attr "mode" "HF"))
+ (eq_attr "sew" "16"))
"tt_ascalon_d8_decode,(tt_ascalon_d8_vec0*3 | tt_ascalon_d8_vec1*3)")
(define_insn_reservation "tt_ascalon_d8_vec_float_divsqrt_single" 10
(and (eq_attr "tune" "tt_ascalon_d8")
(eq_attr "type" "vfdiv,vfsqrt")
- (eq_attr "mode" "SF"))
+ (eq_attr "sew" "32"))
"tt_ascalon_d8_decode,(tt_ascalon_d8_vec0*3 | tt_ascalon_d8_vec1*3)")
(define_insn_reservation "tt_ascalon_d8_vec_float_divsqrt_double" 17
(and (eq_attr "tune" "tt_ascalon_d8")
(eq_attr "type" "vfdiv,vfsqrt")
- (eq_attr "mode" "DF"))
+ (eq_attr "sew" "64"))
"tt_ascalon_d8_decode,(tt_ascalon_d8_vec0*3 | tt_ascalon_d8_vec1*3)")
;; Vector mask operations.
diff --git a/gcc/testsuite/gcc.target/riscv/pr121878.c
b/gcc/testsuite/gcc.target/riscv/pr121878.c
new file mode 100644
index 00000000000..0df58306f58
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/pr121878.c
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-mcpu=tt-ascalon-d8 -mtune=tt-ascalon-d8" } */
+
+/* Verify we don't ICE on the following test case. */
+
+typedef int __attribute__((__vector_size__ (32))) vec;
+vec
+foo (vec x, vec y)
+{
+ return x / y;
+}
