Call check_effective_target_riscv_zvfh_ok rather than
check_effective_target_riscv_zvfh in vx_vf_*run-1-f16.c run tests and ensure
that they are actually run.
Also fix remove_options_for_riscv_zvfh.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmacc-run-1-f16.c: Call
check_effective_target_riscv_zvfh_ok rather than
check_effective_target_riscv_zvfh.
* gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmadd-run-1-f16.c: Likewise.
* gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmsac-run-1-f16.c: Likewise.
* gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmsub-run-1-f16.c: Likewise.
* gcc.target/riscv/rvv/autovec/vx_vf/vf_vfnmacc-run-1-f16.c: Likewise.
* gcc.target/riscv/rvv/autovec/vx_vf/vf_vfnmadd-run-1-f16.c: Likewise.
* gcc.target/riscv/rvv/autovec/vx_vf/vf_vfnmsac-run-1-f16.c: Likewise.
* gcc.target/riscv/rvv/autovec/vx_vf/vf_vfnmsub-run-1-f16.c: Likewise.
* gcc.target/riscv/rvv/autovec/vx_vf/vf_vfwmacc-run-1-f16.c: Likewise.
* gcc.target/riscv/rvv/autovec/vx_vf/vf_vfwmsac-run-1-f16.c: Likewise.
* gcc.target/riscv/rvv/autovec/vx_vf/vf_vfwnmacc-run-1-f16.c: Likewise.
* gcc.target/riscv/rvv/autovec/vx_vf/vf_vfwnmsac-run-1-f16.c: Likewise.
* lib/target-supports.exp (check_effective_target_riscv_zvfh_ok): Append
zvfh instead of v to march.
(remove_options_for_riscv_zvfh): Remove duplicate and
call remove_ rather than add_options_for_riscv_z_ext.
---
.../riscv/rvv/autovec/vx_vf/vf_vfmacc-run-1-f16.c | 2 +-
.../riscv/rvv/autovec/vx_vf/vf_vfmadd-run-1-f16.c | 2 +-
.../riscv/rvv/autovec/vx_vf/vf_vfmsac-run-1-f16.c | 2 +-
.../riscv/rvv/autovec/vx_vf/vf_vfmsub-run-1-f16.c | 2 +-
.../riscv/rvv/autovec/vx_vf/vf_vfnmacc-run-1-f16.c | 2 +-
.../riscv/rvv/autovec/vx_vf/vf_vfnmadd-run-1-f16.c | 2 +-
.../riscv/rvv/autovec/vx_vf/vf_vfnmsac-run-1-f16.c | 2 +-
.../riscv/rvv/autovec/vx_vf/vf_vfnmsub-run-1-f16.c | 2 +-
.../riscv/rvv/autovec/vx_vf/vf_vfwmacc-run-1-f16.c | 2 +-
.../riscv/rvv/autovec/vx_vf/vf_vfwmsac-run-1-f16.c | 2 +-
.../riscv/rvv/autovec/vx_vf/vf_vfwnmacc-run-1-f16.c | 2 +-
.../riscv/rvv/autovec/vx_vf/vf_vfwnmsac-run-1-f16.c | 2 +-
gcc/testsuite/lib/target-supports.exp | 8 ++------
13 files changed, 14 insertions(+), 18 deletions(-)
diff --git
gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmacc-run-1-f16.c
gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmacc-run-1-f16.c
index fd8aa30be17..a54d9a12ecd 100644
--- gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmacc-run-1-f16.c
+++ gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmacc-run-1-f16.c
@@ -1,6 +1,6 @@
/* { dg-do run { target { riscv_v } } } */
/* { dg-require-effective-target riscv_v_ok } */
-/* { dg-require-effective-target riscv_zvfh } */
+/* { dg-require-effective-target riscv_zvfh_ok } */
/* { dg-add-options "riscv_v" } */
/* { dg-add-options "riscv_zvfh" } */
/* { dg-additional-options "--param=fpr2vr-cost=0" } */
diff --git
gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmadd-run-1-f16.c
gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmadd-run-1-f16.c
index 8fd85528899..2289d04e91d 100644
--- gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmadd-run-1-f16.c
+++ gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmadd-run-1-f16.c
@@ -1,6 +1,6 @@
/* { dg-do run { target { riscv_v } } } */
/* { dg-require-effective-target riscv_v_ok } */
-/* { dg-require-effective-target riscv_zvfh } */
+/* { dg-require-effective-target riscv_zvfh_ok } */
/* { dg-add-options "riscv_v" } */
/* { dg-add-options "riscv_zvfh" } */
/* { dg-additional-options "--param=fpr2vr-cost=0" } */
diff --git
gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmsac-run-1-f16.c
gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmsac-run-1-f16.c
index e91fd15a5b7..b6d944cf945 100644
--- gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmsac-run-1-f16.c
+++ gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmsac-run-1-f16.c
@@ -1,6 +1,6 @@
/* { dg-do run { target { riscv_v } } } */
/* { dg-require-effective-target riscv_v_ok } */
-/* { dg-require-effective-target riscv_zvfh } */
+/* { dg-require-effective-target riscv_zvfh_ok } */
/* { dg-add-options "riscv_v" } */
/* { dg-add-options "riscv_zvfh" } */
/* { dg-additional-options "--param=fpr2vr-cost=0" } */
diff --git
gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmsub-run-1-f16.c
gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmsub-run-1-f16.c
index ca7e0db17b5..e9253fe407c 100644
--- gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmsub-run-1-f16.c
+++ gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfmsub-run-1-f16.c
@@ -1,6 +1,6 @@
/* { dg-do run { target { riscv_v } } } */
/* { dg-require-effective-target riscv_v_ok } */
-/* { dg-require-effective-target riscv_zvfh } */
+/* { dg-require-effective-target riscv_zvfh_ok } */
/* { dg-add-options "riscv_v" } */
/* { dg-add-options "riscv_zvfh" } */
/* { dg-additional-options "--param=fpr2vr-cost=0" } */
diff --git
gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfnmacc-run-1-f16.c
gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfnmacc-run-1-f16.c
index b38e8009fd8..397e2834e29 100644
--- gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfnmacc-run-1-f16.c
+++ gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfnmacc-run-1-f16.c
@@ -1,6 +1,6 @@
/* { dg-do run { target { riscv_v } } } */
/* { dg-require-effective-target riscv_v_ok } */
-/* { dg-require-effective-target riscv_zvfh } */
+/* { dg-require-effective-target riscv_zvfh_ok } */
/* { dg-add-options "riscv_v" } */
/* { dg-add-options "riscv_zvfh" } */
/* { dg-additional-options "--param=fpr2vr-cost=0" } */
diff --git
gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfnmadd-run-1-f16.c
gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfnmadd-run-1-f16.c
index fef5d7779a2..6d846a23af7 100644
--- gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfnmadd-run-1-f16.c
+++ gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfnmadd-run-1-f16.c
@@ -1,6 +1,6 @@
/* { dg-do run { target { riscv_v } } } */
/* { dg-require-effective-target riscv_v_ok } */
-/* { dg-require-effective-target riscv_zvfh } */
+/* { dg-require-effective-target riscv_zvfh_ok } */
/* { dg-add-options "riscv_v" } */
/* { dg-add-options "riscv_zvfh" } */
/* { dg-additional-options "--param=fpr2vr-cost=0" } */
diff --git
gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfnmsac-run-1-f16.c
gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfnmsac-run-1-f16.c
index 7951d402c1e..0b4f6e10568 100644
--- gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfnmsac-run-1-f16.c
+++ gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfnmsac-run-1-f16.c
@@ -1,6 +1,6 @@
/* { dg-do run { target { riscv_v } } } */
/* { dg-require-effective-target riscv_v_ok } */
-/* { dg-require-effective-target riscv_zvfh } */
+/* { dg-require-effective-target riscv_zvfh_ok } */
/* { dg-add-options "riscv_v" } */
/* { dg-add-options "riscv_zvfh" } */
/* { dg-additional-options "--param=fpr2vr-cost=0" } */
diff --git
gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfnmsub-run-1-f16.c
gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfnmsub-run-1-f16.c
index d0def86acc5..acc7aa35ebf 100644
--- gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfnmsub-run-1-f16.c
+++ gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfnmsub-run-1-f16.c
@@ -1,6 +1,6 @@
/* { dg-do run { target { riscv_v } } } */
/* { dg-require-effective-target riscv_v_ok } */
-/* { dg-require-effective-target riscv_zvfh } */
+/* { dg-require-effective-target riscv_zvfh_ok } */
/* { dg-add-options "riscv_v" } */
/* { dg-add-options "riscv_zvfh" } */
/* { dg-additional-options "--param=fpr2vr-cost=0" } */
diff --git
gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfwmacc-run-1-f16.c
gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfwmacc-run-1-f16.c
index d4c527abd36..a858d27119b 100644
--- gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfwmacc-run-1-f16.c
+++ gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfwmacc-run-1-f16.c
@@ -1,6 +1,6 @@
/* { dg-do run { target { riscv_v } } } */
/* { dg-require-effective-target riscv_v_ok } */
-/* { dg-require-effective-target riscv_zvfh } */
+/* { dg-require-effective-target riscv_zvfh_ok } */
/* { dg-add-options "riscv_v" } */
/* { dg-add-options "riscv_zvfh" } */
/* { dg-additional-options "--param=fpr2vr-cost=0" } */
diff --git
gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfwmsac-run-1-f16.c
gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfwmsac-run-1-f16.c
index abce2f2c408..a04bd91213a 100644
--- gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfwmsac-run-1-f16.c
+++ gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfwmsac-run-1-f16.c
@@ -1,6 +1,6 @@
/* { dg-do run { target { riscv_v } } } */
/* { dg-require-effective-target riscv_v_ok } */
-/* { dg-require-effective-target riscv_zvfh } */
+/* { dg-require-effective-target riscv_zvfh_ok } */
/* { dg-add-options "riscv_v" } */
/* { dg-add-options "riscv_zvfh" } */
/* { dg-additional-options "--param=fpr2vr-cost=0" } */
diff --git
gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfwnmacc-run-1-f16.c
gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfwnmacc-run-1-f16.c
index ddf49d5b2f2..a00d6206fd9 100644
--- gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfwnmacc-run-1-f16.c
+++ gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfwnmacc-run-1-f16.c
@@ -1,6 +1,6 @@
/* { dg-do run { target { riscv_v } } } */
/* { dg-require-effective-target riscv_v_ok } */
-/* { dg-require-effective-target riscv_zvfh } */
+/* { dg-require-effective-target riscv_zvfh_ok } */
/* { dg-add-options "riscv_v" } */
/* { dg-add-options "riscv_zvfh" } */
/* { dg-additional-options "--param=fpr2vr-cost=0" } */
diff --git
gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfwnmsac-run-1-f16.c
gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfwnmsac-run-1-f16.c
index a8749915569..eeae215c80f 100644
--- gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfwnmsac-run-1-f16.c
+++ gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vf_vfwnmsac-run-1-f16.c
@@ -1,6 +1,6 @@
/* { dg-do run { target { riscv_v } } } */
/* { dg-require-effective-target riscv_v_ok } */
-/* { dg-require-effective-target riscv_zvfh } */
+/* { dg-require-effective-target riscv_zvfh_ok } */
/* { dg-add-options "riscv_v" } */
/* { dg-add-options "riscv_zvfh" } */
/* { dg-additional-options "--param=fpr2vr-cost=0" } */
diff --git gcc/testsuite/lib/target-supports.exp
gcc/testsuite/lib/target-supports.exp
index e8f88852591..b49363caa12 100644
--- gcc/testsuite/lib/target-supports.exp
+++ gcc/testsuite/lib/target-supports.exp
@@ -2342,7 +2342,7 @@ proc check_effective_target_riscv_zvfh_ok { } {
# check if we can execute vector insns with the given hardware or
# simulator
- set gcc_march [regsub {[[:alnum:]]*} [riscv_get_arch] &v]
+ set gcc_march [regsub {[[:alnum:]]*} [riscv_get_arch] &zvfh]
if { [check_runtime ${gcc_march}_zvfh_exec {
int main()
{
@@ -2711,10 +2711,6 @@ proc remove_options_for_riscv_ztso { flags } {
return [remove_options_for_riscv_z_ext ztso $flags]
}
-proc remove_options_for_riscv_zvfh { flags } {
- return [add_options_for_riscv_z_ext zvfh $flags]
-}
-
proc add_options_for_riscv_zvbb { flags } {
return [add_options_for_riscv_z_ext zvbb $flags]
}
@@ -2728,7 +2724,7 @@ proc add_options_for_riscv_zvfh { flags } {
}
proc remove_options_for_riscv_zvfh { flags } {
- return [add_options_for_riscv_z_ext zvfh $flags]
+ return [remove_options_for_riscv_z_ext zvfh $flags]
}
# Return 1 if the target is ia32 or x86_64.
--
2.39.5
