On 24/06/25 10:21 am, Michael Meissner wrote:
> On Mon, Jun 23, 2025 at 07:30:51PM +0530, Surya Kumari Jangala wrote:
>> Hi Mike,
>>
>> On 14/06/25 2:07 pm, Michael Meissner wrote:
>>> This is patch #1 of 4 that adds the support that can be used in developing
>>> GCC
>>> support for future PowerPC processors.
>>
>> Please reword the commit message, perhaps something like:
>> This is patch #1 of 4 that adds support for the option -mcpu=future. This
>> enables
>> future enhancements to GCC for supporting upcoming PowerPC processors.
>
> Ok.
>
>>> diff --git a/gcc/config/rs6000/rs6000-cpus.def
>>> b/gcc/config/rs6000/rs6000-cpus.def
>>> index 4a1037616d7..228d0b5e7b5 100644
>>> --- a/gcc/config/rs6000/rs6000-cpus.def
>>> +++ b/gcc/config/rs6000/rs6000-cpus.def
>>> @@ -83,6 +83,9 @@
>>> #define POWER11_MASKS_SERVER (ISA_3_1_MASKS_SERVER \
>>> | OPTION_MASK_POWER11)
>>>
>>> +#define FUTURE_MASKS_SERVER (POWER11_MASKS_SERVER
>>> \
>>> + | OPTION_MASK_FUTURE)
>>> +
>>> /* Flags that need to be turned off if -mno-vsx. */
>>> #define OTHER_VSX_VECTOR_MASKS (OPTION_MASK_EFFICIENT_UNALIGNED_VSX
>>> \
>>> | OPTION_MASK_FLOAT128_KEYWORD \
>>> @@ -119,6 +122,7 @@
>>> | OPTION_MASK_FLOAT128_HW \
>>> | OPTION_MASK_FLOAT128_KEYWORD \
>>> | OPTION_MASK_FPRND \
>>> + | OPTION_MASK_FUTURE \
>>> | OPTION_MASK_POWER10 \
>>> | OPTION_MASK_POWER11 \
>>
>> Please add OPTION_MASK_FUTURE after OPTION_MASK_POWER11.
>
> The style in rs6000-cpus.def for the POWERPC_MASKS macro is to have all of the
> option masks be sorted alphabetically. This macro is a list of all of the
> options that need to be toggled as setting ISA bits when using either:
>
> #pragma GCC target "..."
> or
> __attribute__((__target__("...")))
>
> But if desired, I can certainly change it.
Ok. Please retain your original code.
>
>>> | OPTION_MASK_P10_FUSION \
>>> @@ -249,6 +253,7 @@ RS6000_CPU ("power9", PROCESSOR_POWER9, MASK_POWERPC64
>>> | ISA_3_0_MASKS_SERVER
>>> | OPTION_MASK_HTM)
>>> RS6000_CPU ("power10", PROCESSOR_POWER10, MASK_POWERPC64 |
>>> ISA_3_1_MASKS_SERVER)
>>> RS6000_CPU ("power11", PROCESSOR_POWER11, MASK_POWERPC64 |
>>> POWER11_MASKS_SERVER)
>>> +RS6000_CPU ("future", PROCESSOR_FUTURE, MASK_POWERPC64 |
>>> FUTURE_MASKS_SERVER)
>>> RS6000_CPU ("powerpc", PROCESSOR_POWERPC, 0)
>>> RS6000_CPU ("powerpc64", PROCESSOR_POWERPC64, OPTION_MASK_PPC_GFXOPT
>>> | MASK_POWERPC64)
>>> diff --git a/gcc/config/rs6000/rs6000-opts.h
>>> b/gcc/config/rs6000/rs6000-opts.h
>>> index c31d2975f04..3983d463e31 100644
>>> --- a/gcc/config/rs6000/rs6000-opts.h
>>> +++ b/gcc/config/rs6000/rs6000-opts.h
>>> @@ -63,6 +63,7 @@ enum processor_type
>>> PROCESSOR_POWER9,
>>> PROCESSOR_POWER10,
>>> PROCESSOR_POWER11,
>>> + PROCESSOR_FUTURE,
>>>
>>> PROCESSOR_RS64A,
>>> PROCESSOR_MPCCORE,
>>> diff --git a/gcc/config/rs6000/rs6000-tables.opt
>>> b/gcc/config/rs6000/rs6000-tables.opt
>>> index f5bbed5ea74..518324e7aea 100644
>>> --- a/gcc/config/rs6000/rs6000-tables.opt
>>> +++ b/gcc/config/rs6000/rs6000-tables.opt
>>> @@ -189,14 +189,17 @@ EnumValue
>>> Enum(rs6000_cpu_opt_value) String(power11) Value(53)
>>>
>>> EnumValue
>>> -Enum(rs6000_cpu_opt_value) String(powerpc) Value(54)
>>> +Enum(rs6000_cpu_opt_value) String(future) Value(54)
>>>
>>> EnumValue
>>> -Enum(rs6000_cpu_opt_value) String(powerpc64) Value(55)
>>> +Enum(rs6000_cpu_opt_value) String(powerpc) Value(55)
>>>
>>> EnumValue
>>> -Enum(rs6000_cpu_opt_value) String(powerpc64le) Value(56)
>>> +Enum(rs6000_cpu_opt_value) String(powerpc64) Value(56)
>>>
>>> EnumValue
>>> -Enum(rs6000_cpu_opt_value) String(rs64) Value(57)
>>> +Enum(rs6000_cpu_opt_value) String(powerpc64le) Value(57)
>>> +
>>> +EnumValue
>>> +Enum(rs6000_cpu_opt_value) String(rs64) Value(58)
>>>
>>> diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
>>> index 7ee26e52b13..141d53b1a12 100644
>>> --- a/gcc/config/rs6000/rs6000.cc
>>> +++ b/gcc/config/rs6000/rs6000.cc
>>> @@ -1066,7 +1066,7 @@ struct processor_costs power9_cost = {
>>> COSTS_N_INSNS (3), /* SF->DF convert */
>>> };
>>>
>>> -/* Instruction costs on Power10/Power11 processors. */
>>> +/* Instruction costs on Power10/Power11/future processors. */
>>> static const
>>> struct processor_costs power10_cost = {
>>> COSTS_N_INSNS (2), /* mulsi */
>>> @@ -4388,7 +4388,8 @@ rs6000_option_override_internal (bool global_init_p)
>>> if (!(rs6000_isa_flags_explicit & OPTION_MASK_P10_FUSION))
>>> {
>>> if (rs6000_tune == PROCESSOR_POWER10
>>> - || rs6000_tune == PROCESSOR_POWER11)
>>> + || rs6000_tune == PROCESSOR_POWER11
>>> + || rs6000_tune == PROCESSOR_FUTURE)
>>> rs6000_isa_flags |= OPTION_MASK_P10_FUSION;
>>> else
>>> rs6000_isa_flags &= ~OPTION_MASK_P10_FUSION;
>>> @@ -4418,6 +4419,7 @@ rs6000_option_override_internal (bool global_init_p)
>>> && rs6000_tune != PROCESSOR_POWER9
>>> && rs6000_tune != PROCESSOR_POWER10
>>> && rs6000_tune != PROCESSOR_POWER11
>>> + && rs6000_tune != PROCESSOR_FUTURE
>>> && rs6000_tune != PROCESSOR_PPCA2
>>> && rs6000_tune != PROCESSOR_CELL
>>> && rs6000_tune != PROCESSOR_PPC476);
>>> @@ -4433,6 +4435,7 @@ rs6000_option_override_internal (bool global_init_p)
>>> || rs6000_tune == PROCESSOR_POWER9
>>> || rs6000_tune == PROCESSOR_POWER10
>>> || rs6000_tune == PROCESSOR_POWER11
>>> + || rs6000_tune == PROCESSOR_FUTURE
>>> || rs6000_tune == PROCESSOR_PPCE500MC
>>> || rs6000_tune == PROCESSOR_PPCE500MC64
>>> || rs6000_tune == PROCESSOR_PPCE5500
>>> @@ -4733,6 +4736,7 @@ rs6000_option_override_internal (bool global_init_p)
>>>
>>> case PROCESSOR_POWER10:
>>> case PROCESSOR_POWER11:
>>> + case PROCESSOR_FUTURE:
>>> rs6000_cost = &power10_cost;
>>> break;
>>>
>>> @@ -5905,6 +5909,8 @@ rs6000_machine_from_flags (void)
>>> flags &= ~(OPTION_MASK_PPC_GFXOPT | OPTION_MASK_PPC_GPOPT |
>>> OPTION_MASK_ISEL
>>> | OPTION_MASK_ALTIVEC);
>>>
>>> + if ((flags & (FUTURE_MASKS_SERVER & ~ISA_3_1_MASKS_SERVER)) != 0)
>>
>> The test should be against POWER11_MASKS_SERVER, not ISA_3_1_MASKS_SERVER.
>>
>>> + return "future";
>>> if ((flags & (POWER11_MASKS_SERVER & ~ISA_3_1_MASKS_SERVER)) != 0)
>>> return "power11";
>>> if ((flags & (ISA_3_1_MASKS_SERVER & ~ISA_3_0_MASKS_SERVER)) != 0)
>>> @@ -10155,6 +10161,7 @@ rs6000_reassociation_width (unsigned int opc
>>> ATTRIBUTE_UNUSED,
>>> case PROCESSOR_POWER9:
>>> case PROCESSOR_POWER10:
>>> case PROCESSOR_POWER11:
>>> + case PROCESSOR_FUTURE:
>>> if (DECIMAL_FLOAT_MODE_P (mode))
>>> return 1;
>>> if (VECTOR_MODE_P (mode))
>>> @@ -18197,7 +18204,8 @@ rs6000_adjust_cost (rtx_insn *insn, int dep_type,
>>> rtx_insn *dep_insn, int cost,
>>> /* Separate a load from a narrower, dependent store. */
>>> if ((rs6000_sched_groups || rs6000_tune == PROCESSOR_POWER9
>>> || rs6000_tune == PROCESSOR_POWER10
>>> - || rs6000_tune == PROCESSOR_POWER11)
>>> + || rs6000_tune == PROCESSOR_POWER11
>>> + || rs6000_tune == PROCESSOR_FUTURE)
>>> && GET_CODE (PATTERN (insn)) == SET
>>> && GET_CODE (PATTERN (dep_insn)) == SET
>>> && MEM_P (XEXP (PATTERN (insn), 1))
>>> @@ -18237,6 +18245,7 @@ rs6000_adjust_cost (rtx_insn *insn, int dep_type,
>>> rtx_insn *dep_insn, int cost,
>>> || rs6000_tune == PROCESSOR_POWER9
>>> || rs6000_tune == PROCESSOR_POWER10
>>> || rs6000_tune == PROCESSOR_POWER11
>>> + || rs6000_tune == PROCESSOR_FUTURE
>>> || rs6000_tune == PROCESSOR_CELL)
>>> && recog_memoized (dep_insn)
>>> && (INSN_CODE (dep_insn) >= 0))
>>> @@ -18812,6 +18821,7 @@ rs6000_issue_rate (void)
>>> return 6;
>>> case PROCESSOR_POWER10:
>>> case PROCESSOR_POWER11:
>>> + case PROCESSOR_FUTURE:
>>> return 8;
>>> default:
>>> return 1;
>>> @@ -19527,10 +19537,11 @@ rs6000_sched_reorder (FILE *dump
>>> ATTRIBUTE_UNUSED, int sched_verbose,
>>> if (rs6000_tune == PROCESSOR_POWER6)
>>> load_store_pendulum = 0;
>>>
>>> - /* Do Power10/Power11 dependent reordering. */
>>> + /* Do Power10/Power11/future dependent reordering. */
>>> if (last_scheduled_insn
>>> && (rs6000_tune == PROCESSOR_POWER10
>>> - || rs6000_tune == PROCESSOR_POWER11))
>>> + || rs6000_tune == PROCESSOR_POWER11
>>> + || rs6000_tune == PROCESSOR_FUTURE))
>>> power10_sched_reorder (ready, n_ready - 1);
>>>
>>> return rs6000_issue_rate ();
>>> @@ -19554,10 +19565,11 @@ rs6000_sched_reorder2 (FILE *dump, int
>>> sched_verbose, rtx_insn **ready,
>>> && recog_memoized (last_scheduled_insn) >= 0)
>>> return power9_sched_reorder2 (ready, *pn_ready - 1);
>>>
>>> - /* Do Power10/Power11 dependent reordering. */
>>> + /* Do Power10/Power11/future dependent reordering. */
>>> if (last_scheduled_insn
>>> && (rs6000_tune == PROCESSOR_POWER10
>>> - || rs6000_tune == PROCESSOR_POWER11))
>>> + || rs6000_tune == PROCESSOR_POWER11
>>> + || rs6000_tune == PROCESSOR_FUTURE))
>>> return power10_sched_reorder (ready, *pn_ready - 1);
>>>
>>> return cached_can_issue_more;
>>> @@ -22780,7 +22792,8 @@ rs6000_register_move_cost (machine_mode mode,
>>> out to be a nop. */
>>> if (rs6000_tune == PROCESSOR_POWER9
>>> || rs6000_tune == PROCESSOR_POWER10
>>> - || rs6000_tune == PROCESSOR_POWER11)
>>> + || rs6000_tune == PROCESSOR_POWER11
>>> + || rs6000_tune == PROCESSOR_FUTURE)
>>> ret = 3 * hard_regno_nregs (FIRST_GPR_REGNO, mode);
>>> else
>>> ret = 4 * hard_regno_nregs (FIRST_GPR_REGNO, mode);
>>> @@ -24450,6 +24463,7 @@ static struct rs6000_opt_mask const
>>> rs6000_opt_masks[] =
>>> { "float128", OPTION_MASK_FLOAT128_KEYWORD, false,
>>> true },
>>> { "float128-hardware", OPTION_MASK_FLOAT128_HW, false, true },
>>> { "fprnd", OPTION_MASK_FPRND, false,
>>> true },
>>> + { "future", OPTION_MASK_FUTURE, false,
>>> false },
>>
>> Please add this line after the "power11" line.
>>
>>
>>> { "power10", OPTION_MASK_POWER10, false,
>>> true },
>>> { "power11", OPTION_MASK_POWER11, false,
>>> false },
>>> { "hard-dfp", OPTION_MASK_DFP, false,
>>> true },
>>> diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h
>>> index db6112a09e1..76c6cd1ab8e 100644
>>> --- a/gcc/config/rs6000/rs6000.h
>>> +++ b/gcc/config/rs6000/rs6000.h
>>> @@ -101,6 +101,7 @@
>>> you make changes here, make them also there. */
>>> #define ASM_CPU_SPEC \
>>> "%{mcpu=native: %(asm_cpu_native); \
>>> + mcpu=future: -mfuture; \
>>> mcpu=power11: -mpower11; \
>>> mcpu=power10: -mpower10; \
>>> mcpu=power9: -mpower9; \
>>> diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
>>> index 9c718ca2a22..605047f99a8 100644
>>> --- a/gcc/config/rs6000/rs6000.md
>>> +++ b/gcc/config/rs6000/rs6000.md
>>> @@ -364,7 +364,7 @@ (define_attr "cpu"
>>> ppc750,ppc7400,ppc7450,
>>> ppc403,ppc405,ppc440,ppc476,
>>>
>>> ppc8540,ppc8548,ppce300c2,ppce300c3,ppce500mc,ppce500mc64,ppce5500,ppce6500,
>>> - power4,power5,power6,power7,power8,power9,power10,power11,
>>> + power4,power5,power6,power7,power8,power9,power10,power11,future,
>>> rs64a,mpccore,cell,ppca2,titan"
>>> (const (symbol_ref "(enum attr_cpu) rs6000_tune")))
>>>
>>> diff --git a/gcc/config/rs6000/rs6000.opt b/gcc/config/rs6000/rs6000.opt
>>> index 88cf16ca581..7e1af7120bc 100644
>>> --- a/gcc/config/rs6000/rs6000.opt
>>> +++ b/gcc/config/rs6000/rs6000.opt
>>> @@ -634,6 +634,12 @@ mieee128-constant
>>> Target Var(TARGET_IEEE128_CONSTANT) Init(1) Save
>>> Generate (do not generate) code that uses the LXVKQ instruction.
>>>
>>> +;; Users should not use -mfuture, but we need to use a bit to identify when
>>> +;; the user changes the default cpu via #pragma GCC target("cpu=future")
>>> +;; and then resets it later.
>>> +mfuture
>>> +Target Undocumented Mask(FUTURE) Var(rs6000_isa_flags) WarnRemoved
>>> +
>>
>> Please add this after 'mpower11'
>
> Historically, we have always added new flag bits at the end, which is what I
> did in this patch. The -mpower11 option should have been added after
> -mieee128-constant (-mprefixed, -mpcrel, -mpcrel-opt, -mmma,
> -msplat-* are all power10 options).
Ok.
Regards,
Surya
>
> Granted -mrelative-jumptables, -mrop-protect, and -mprivileged are not power10
> specific, but they were added after the basic power10 support was added
> (hence,
> add new ISA options at the end).
>
> I mentioned in my other reply, that I have a set of patches that separates the
> option bits (i.e. -mpopcntb, -mcmpb, etc.) from the ISA bits set via
> -mcpu=<xxx>. If/when those sets of patches go in, then it allows use to
> remove
> these fake option bits. This patch would allow us to delete:
>
> -mpower8-internal
> -mpower10
> -mpower11
> -mfuture
>
>
>> Also, in the routine expand_compare_loop(), we should handle PROCESSOR_FUTURE
>> when computing max_bytes.
>
> Ok, I'll look at it.
>
>>
>> -Surya
>>
>>> ; Documented parameters
>>>
>>> -param=rs6000-vect-unroll-limit=
>>
>
