On 6/17/25 7:15 AM, Paul-Antoine Arras wrote:
This is part of my vector-scalar FMA series. See:
https://gcc.gnu.org/pipermail/gcc-patches/2025-March/679513.html
https://gcc.gnu.org/pipermail/gcc-patches/2025-June/685624.html
The attached patch handles vfmacc and vfmsac. However I ran into an
issue while writing testcases. Since the add and acc variants share the
same RTL patterns, the only difference being operand constraints, RA is
free to pick either of the two, which makes it difficult to test in a
straightforward and reliable way.
I managed to get appropriate testcases in vf-3-* and vf-4-* by making
the loop body longer and register pressure higher. Now I haven't found a
simple equivalent either for vf-1-* and vf-2-* or for the run tests.
The attempt shown in the current patch (e.g. vf-1-f64) exercises the
right pattern (*pred_mul_addrvvm4df_scalar_undef) but the wrong
alternative (got 2 while wanting to test 3).
Any suggestion would be appreciated!
Yea, I expect the testsuite aspects to be tough and fragile since final
instruction selection is based on register allocation which obviously
can be influenced by all kinds of things. If you're not in the call
today, I'll raise the topic to see if there's any suggestions.
Jeff
