From: Pan Li <pan2...@intel.com>

Add asm dump check test for vec_duplicate + vmul.vv combine to vmul.vx,
with the GR2VR cost is 0, 2 and 15.

The below test suites are passed for this patch.
* The rv64gcv fully regression test.

gcc/testsuite/ChangeLog:

        * gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i16.c: Add asm check
        for vmul.vx combine.
        * gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i32.c: Ditto.
        * gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i64.c: Ditto.
        * gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i8.c: Ditto.
        * gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i16.c: Ditto.
        * gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i32.c: Ditto.
        * gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i64.c: Ditto.
        * gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i8.c: Ditto.
        * gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i16.c: Ditto.
        * gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i32.c: Ditto.
        * gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i64.c: Ditto.
        * gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i8.c: Ditto.
        * gcc.target/riscv/rvv/autovec/vx_vf/vx_binary_data.h: Add test
        data for vmul run test.
        * gcc.target/riscv/rvv/autovec/vx_vf/vx_vmul-run-1-i16.c: New test.
        * gcc.target/riscv/rvv/autovec/vx_vf/vx_vmul-run-1-i32.c: New test.
        * gcc.target/riscv/rvv/autovec/vx_vf/vx_vmul-run-1-i64.c: New test.
        * gcc.target/riscv/rvv/autovec/vx_vf/vx_vmul-run-1-i8.c: New test.

Signed-off-by: Pan Li <pan2...@intel.com>
---
 .../riscv/rvv/autovec/vx_vf/vx-1-i16.c        |   2 +
 .../riscv/rvv/autovec/vx_vf/vx-1-i32.c        |   2 +
 .../riscv/rvv/autovec/vx_vf/vx-1-i64.c        |   2 +
 .../riscv/rvv/autovec/vx_vf/vx-1-i8.c         |   2 +
 .../riscv/rvv/autovec/vx_vf/vx-2-i16.c        |   2 +
 .../riscv/rvv/autovec/vx_vf/vx-2-i32.c        |   2 +
 .../riscv/rvv/autovec/vx_vf/vx-2-i64.c        |   2 +
 .../riscv/rvv/autovec/vx_vf/vx-2-i8.c         |   2 +
 .../riscv/rvv/autovec/vx_vf/vx-3-i16.c        |   2 +
 .../riscv/rvv/autovec/vx_vf/vx-3-i32.c        |   2 +
 .../riscv/rvv/autovec/vx_vf/vx-3-i64.c        |   2 +
 .../riscv/rvv/autovec/vx_vf/vx-3-i8.c         |   2 +
 .../riscv/rvv/autovec/vx_vf/vx_binary_data.h  | 196 ++++++++++++++++++
 .../rvv/autovec/vx_vf/vx_vmul-run-1-i16.c     |  15 ++
 .../rvv/autovec/vx_vf/vx_vmul-run-1-i32.c     |  15 ++
 .../rvv/autovec/vx_vf/vx_vmul-run-1-i64.c     |  15 ++
 .../rvv/autovec/vx_vf/vx_vmul-run-1-i8.c      |  15 ++
 17 files changed, 280 insertions(+)
 create mode 100644 
gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmul-run-1-i16.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmul-run-1-i32.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmul-run-1-i64.c
 create mode 100644 
gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmul-run-1-i8.c

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i16.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i16.c
index b9be0f674ae..144d1bad6af 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i16.c
@@ -11,6 +11,7 @@ DEF_VX_BINARY_REVERSE_CASE_0_WRAP(T, -, rsub);
 DEF_VX_BINARY_CASE_0_WRAP(T, &, and)
 DEF_VX_BINARY_CASE_0_WRAP(T, |, or)
 DEF_VX_BINARY_CASE_0_WRAP(T, ^, xor)
+DEF_VX_BINARY_CASE_0_WRAP(T, *, mul)
 
 /* { dg-final { scan-assembler-times {vadd.vx} 1 } } */
 /* { dg-final { scan-assembler-times {vsub.vx} 1 } } */
@@ -18,3 +19,4 @@ DEF_VX_BINARY_CASE_0_WRAP(T, ^, xor)
 /* { dg-final { scan-assembler-times {vand.vx} 1 } } */
 /* { dg-final { scan-assembler-times {vor.vx} 1 } } */
 /* { dg-final { scan-assembler-times {vxor.vx} 1 } } */
+/* { dg-final { scan-assembler-times {vmul.vx} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i32.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i32.c
index 2a84980cb50..74d35d13cf6 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i32.c
@@ -11,6 +11,7 @@ DEF_VX_BINARY_REVERSE_CASE_0_WRAP(T, -, rsub);
 DEF_VX_BINARY_CASE_0_WRAP(T, &, and)
 DEF_VX_BINARY_CASE_0_WRAP(T, |, or)
 DEF_VX_BINARY_CASE_0_WRAP(T, ^, xor)
+DEF_VX_BINARY_CASE_0_WRAP(T, *, mul)
 
 /* { dg-final { scan-assembler-times {vadd.vx} 1 } } */
 /* { dg-final { scan-assembler-times {vsub.vx} 1 } } */
@@ -18,3 +19,4 @@ DEF_VX_BINARY_CASE_0_WRAP(T, ^, xor)
 /* { dg-final { scan-assembler-times {vand.vx} 1 } } */
 /* { dg-final { scan-assembler-times {vor.vx} 1 } } */
 /* { dg-final { scan-assembler-times {vxor.vx} 1 } } */
+/* { dg-final { scan-assembler-times {vmul.vx} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i64.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i64.c
index 9c7ea5fa413..ac512ff7fbd 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i64.c
@@ -11,6 +11,7 @@ DEF_VX_BINARY_REVERSE_CASE_0_WRAP(T, -, rsub);
 DEF_VX_BINARY_CASE_0_WRAP(T, &, and)
 DEF_VX_BINARY_CASE_0_WRAP(T, |, or)
 DEF_VX_BINARY_CASE_0_WRAP(T, ^, xor)
+DEF_VX_BINARY_CASE_0_WRAP(T, *, mul)
 
 /* { dg-final { scan-assembler-times {vadd.vx} 1 } } */
 /* { dg-final { scan-assembler-times {vsub.vx} 1 } } */
@@ -18,3 +19,4 @@ DEF_VX_BINARY_CASE_0_WRAP(T, ^, xor)
 /* { dg-final { scan-assembler-times {vand.vx} 1 } } */
 /* { dg-final { scan-assembler-times {vor.vx} 1 } } */
 /* { dg-final { scan-assembler-times {vxor.vx} 1 } } */
+/* { dg-final { scan-assembler-times {vmul.vx} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i8.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i8.c
index fc23f1c49f9..4f7b675ead5 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-i8.c
@@ -11,6 +11,7 @@ DEF_VX_BINARY_REVERSE_CASE_0_WRAP(T, -, rsub);
 DEF_VX_BINARY_CASE_0_WRAP(T, &, and)
 DEF_VX_BINARY_CASE_0_WRAP(T, |, or)
 DEF_VX_BINARY_CASE_0_WRAP(T, ^, xor)
+DEF_VX_BINARY_CASE_0_WRAP(T, *, mul)
 
 /* { dg-final { scan-assembler-times {vadd.vx} 1 } } */
 /* { dg-final { scan-assembler-times {vsub.vx} 1 } } */
@@ -18,3 +19,4 @@ DEF_VX_BINARY_CASE_0_WRAP(T, ^, xor)
 /* { dg-final { scan-assembler-times {vand.vx} 1 } } */
 /* { dg-final { scan-assembler-times {vor.vx} 1 } } */
 /* { dg-final { scan-assembler-times {vxor.vx} 1 } } */
+/* { dg-final { scan-assembler-times {vmul.vx} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i16.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i16.c
index de250864e2d..075c8be75fd 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i16.c
@@ -11,6 +11,7 @@ DEF_VX_BINARY_REVERSE_CASE_0_WRAP(T, -, rsub)
 DEF_VX_BINARY_CASE_0_WRAP(T, &, and)
 DEF_VX_BINARY_CASE_0_WRAP(T, |, or)
 DEF_VX_BINARY_CASE_0_WRAP(T, ^, xor)
+DEF_VX_BINARY_CASE_0_WRAP(T, *, mul)
 
 /* { dg-final { scan-assembler-not {vadd.vx} } } */
 /* { dg-final { scan-assembler-not {vsub.vx} } } */
@@ -18,3 +19,4 @@ DEF_VX_BINARY_CASE_0_WRAP(T, ^, xor)
 /* { dg-final { scan-assembler-not {vand.vx} } } */
 /* { dg-final { scan-assembler-not {vor.vx} } } */
 /* { dg-final { scan-assembler-not {vxor.vx} } } */
+/* { dg-final { scan-assembler-not {vmul.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i32.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i32.c
index 5cac7c685f6..595479cc9ff 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i32.c
@@ -11,6 +11,7 @@ DEF_VX_BINARY_REVERSE_CASE_0_WRAP(T, -, rsub)
 DEF_VX_BINARY_CASE_0_WRAP(T, &, and)
 DEF_VX_BINARY_CASE_0_WRAP(T, |, or)
 DEF_VX_BINARY_CASE_0_WRAP(T, ^, xor)
+DEF_VX_BINARY_CASE_0_WRAP(T, *, mul)
 
 /* { dg-final { scan-assembler-not {vadd.vx} } } */
 /* { dg-final { scan-assembler-not {vsub.vx} } } */
@@ -18,3 +19,4 @@ DEF_VX_BINARY_CASE_0_WRAP(T, ^, xor)
 /* { dg-final { scan-assembler-not {vand.vx} } } */
 /* { dg-final { scan-assembler-not {vor.vx} } } */
 /* { dg-final { scan-assembler-not {vxor.vx} } } */
+/* { dg-final { scan-assembler-not {vmul.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i64.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i64.c
index 4b2885a0da9..7b6fcbfa7a6 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i64.c
@@ -11,6 +11,7 @@ DEF_VX_BINARY_REVERSE_CASE_0_WRAP(T, -, rsub)
 DEF_VX_BINARY_CASE_0_WRAP(T, &, and)
 DEF_VX_BINARY_CASE_0_WRAP(T, |, or)
 DEF_VX_BINARY_CASE_0_WRAP(T, ^, xor)
+DEF_VX_BINARY_CASE_0_WRAP(T, *, mul)
 
 /* { dg-final { scan-assembler-not {vadd.vx} } } */
 /* { dg-final { scan-assembler-not {vsub.vx} } } */
@@ -18,3 +19,4 @@ DEF_VX_BINARY_CASE_0_WRAP(T, ^, xor)
 /* { dg-final { scan-assembler-not {vand.vx} } } */
 /* { dg-final { scan-assembler-not {vor.vx} } } */
 /* { dg-final { scan-assembler-not {vxor.vx} } } */
+/* { dg-final { scan-assembler-not {vmul.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i8.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i8.c
index e14683198e5..55fc717a61a 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-i8.c
@@ -11,6 +11,7 @@ DEF_VX_BINARY_REVERSE_CASE_0_WRAP(T, -, rsub)
 DEF_VX_BINARY_CASE_0_WRAP(T, &, and)
 DEF_VX_BINARY_CASE_0_WRAP(T, |, or)
 DEF_VX_BINARY_CASE_0_WRAP(T, ^, xor)
+DEF_VX_BINARY_CASE_0_WRAP(T, *, mul)
 
 /* { dg-final { scan-assembler-not {vadd.vx} } } */
 /* { dg-final { scan-assembler-not {vsub.vx} } } */
@@ -18,3 +19,4 @@ DEF_VX_BINARY_CASE_0_WRAP(T, ^, xor)
 /* { dg-final { scan-assembler-not {vand.vx} } } */
 /* { dg-final { scan-assembler-not {vor.vx} } } */
 /* { dg-final { scan-assembler-not {vxor.vx} } } */
+/* { dg-final { scan-assembler-not {vmul.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i16.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i16.c
index d9e6e7b0389..bec6b3aba1a 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i16.c
@@ -11,6 +11,7 @@ DEF_VX_BINARY_REVERSE_CASE_0_WRAP(T, -, rsub)
 DEF_VX_BINARY_CASE_0_WRAP(T, &, and)
 DEF_VX_BINARY_CASE_0_WRAP(T, |, or)
 DEF_VX_BINARY_CASE_0_WRAP(T, ^, xor)
+DEF_VX_BINARY_CASE_0_WRAP(T, *, mul)
 
 /* { dg-final { scan-assembler-not {vadd.vx} } } */
 /* { dg-final { scan-assembler-not {vsub.vx} } } */
@@ -18,3 +19,4 @@ DEF_VX_BINARY_CASE_0_WRAP(T, ^, xor)
 /* { dg-final { scan-assembler-not {vand.vx} } } */
 /* { dg-final { scan-assembler-not {vor.vx} } } */
 /* { dg-final { scan-assembler-not {vxor.vx} } } */
+/* { dg-final { scan-assembler-not {vmul.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i32.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i32.c
index 13d219ec73a..98fce52dd39 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i32.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i32.c
@@ -11,6 +11,7 @@ DEF_VX_BINARY_REVERSE_CASE_0_WRAP(T, -, rsub)
 DEF_VX_BINARY_CASE_0_WRAP(T, &, and)
 DEF_VX_BINARY_CASE_0_WRAP(T, |, or)
 DEF_VX_BINARY_CASE_0_WRAP(T, ^, xor)
+DEF_VX_BINARY_CASE_0_WRAP(T, *, mul)
 
 /* { dg-final { scan-assembler-not {vadd.vx} } } */
 /* { dg-final { scan-assembler-not {vsub.vx} } } */
@@ -18,3 +19,4 @@ DEF_VX_BINARY_CASE_0_WRAP(T, ^, xor)
 /* { dg-final { scan-assembler-not {vand.vx} } } */
 /* { dg-final { scan-assembler-not {vor.vx} } } */
 /* { dg-final { scan-assembler-not {vxor.vx} } } */
+/* { dg-final { scan-assembler-not {vmul.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i64.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i64.c
index 037a713a60d..48dd57a300b 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i64.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i64.c
@@ -11,6 +11,7 @@ DEF_VX_BINARY_REVERSE_CASE_0_WRAP(T, -, rsub)
 DEF_VX_BINARY_CASE_0_WRAP(T, &, and)
 DEF_VX_BINARY_CASE_0_WRAP(T, |, or)
 DEF_VX_BINARY_CASE_0_WRAP(T, ^, xor)
+DEF_VX_BINARY_CASE_0_WRAP(T, *, mul)
 
 /* { dg-final { scan-assembler-not {vadd.vx} } } */
 /* { dg-final { scan-assembler-not {vsub.vx} } } */
@@ -18,3 +19,4 @@ DEF_VX_BINARY_CASE_0_WRAP(T, ^, xor)
 /* { dg-final { scan-assembler-not {vand.vx} } } */
 /* { dg-final { scan-assembler-not {vor.vx} } } */
 /* { dg-final { scan-assembler-not {vxor.vx} } } */
+/* { dg-final { scan-assembler-not {vmul.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i8.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i8.c
index c97fff4b09f..9bdce829fb9 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-i8.c
@@ -11,6 +11,7 @@ DEF_VX_BINARY_REVERSE_CASE_0_WRAP(T, -, rsub)
 DEF_VX_BINARY_CASE_0_WRAP(T, &, and)
 DEF_VX_BINARY_CASE_0_WRAP(T, |, or)
 DEF_VX_BINARY_CASE_0_WRAP(T, ^, xor)
+DEF_VX_BINARY_CASE_0_WRAP(T, *, mul)
 
 /* { dg-final { scan-assembler-not {vadd.vx} } } */
 /* { dg-final { scan-assembler-not {vsub.vx} } } */
@@ -18,3 +19,4 @@ DEF_VX_BINARY_CASE_0_WRAP(T, ^, xor)
 /* { dg-final { scan-assembler-not {vand.vx} } } */
 /* { dg-final { scan-assembler-not {vor.vx} } } */
 /* { dg-final { scan-assembler-not {vxor.vx} } } */
+/* { dg-final { scan-assembler-not {vmul.vx} } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_binary_data.h 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_binary_data.h
index 60f47f864bc..c7289ac9144 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_binary_data.h
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_binary_data.h
@@ -2358,4 +2358,200 @@ uint64_t TEST_BINARY_DATA(uint64_t, xor)[][3][N] =
   },
 };
 
+int8_t TEST_BINARY_DATA(int8_t, mul)[][3][N] =
+{
+  {
+    { 1 },
+    {
+       0,  0,  0,  0,
+       1,  1,  1,  1,
+      -1, -1, -1, -1,
+      -2, -2, -2, -2,
+    },
+    {
+       0,  0,  0,  0,
+       1,  1,  1,  1,
+      -1, -1, -1, -1,
+      -2, -2, -2, -2,
+    },
+  },
+  {
+    { 127 },
+    {
+         0,    0,    0,    0,
+        -1,   -1,   -1,   -1,
+      -128, -128, -128, -128,
+        -2,   -2,   -2,   -2,
+    },
+    {
+         0,    0,    0,    0,
+      -127, -127, -127, -127,
+      -128, -128, -128, -128,
+         2,    2,    2,    2,
+    },
+  },
+  {
+    { -128 },
+    {
+         0,    0,    0,    0,
+         1,    1,    1,    1,
+       127,  127,  127,  127,
+         2,    2,    2,    2,
+    },
+    {
+         0,    0,    0,    0,
+      -128, -128, -128, -128,
+      -128, -128, -128, -128,
+         0,    0,    0,    0,
+    },
+  },
+};
+
+int16_t TEST_BINARY_DATA(int16_t, mul)[][3][N] =
+{
+  {
+    { 1 },
+    {
+       0,  0,  0,  0,
+       1,  1,  1,  1,
+      -1, -1, -1, -1,
+      -2, -2, -2, -2,
+    },
+    {
+       0,  0,  0,  0,
+       1,  1,  1,  1,
+      -1, -1, -1, -1,
+      -2, -2, -2, -2,
+    },
+  },
+  {
+    { 32767 },
+    {
+           0,      0,      0,      0,
+          -1,     -1,     -1,     -1,
+      -32768, -32768, -32768, -32768,
+          -2,     -2,     -2,     -2,
+    },
+    {
+           0,      0,      0,      0,
+      -32767, -32767, -32767, -32767,
+      -32768, -32768, -32768, -32768,
+           2,      2,      2,      2,
+    },
+  },
+  {
+    { -32768 },
+    {
+           0,      0,      0,      0,
+           1,      1,      1,      1,
+       32767,  32767,  32767,  32767,
+           2,      2,      2,      2,
+    },
+    {
+           0,      0,      0,      0,
+      -32768, -32768, -32768, -32768,
+      -32768, -32768, -32768, -32768,
+           0,      0,      0,      0,
+    },
+  },
+};
+
+int32_t TEST_BINARY_DATA(int32_t, mul)[][3][N] =
+{
+  {
+    { 1 },
+    {
+       0,  0,  0,  0,
+       1,  1,  1,  1,
+      -1, -1, -1, -1,
+      -2, -2, -2, -2,
+    },
+    {
+       0,  0,  0,  0,
+       1,  1,  1,  1,
+      -1, -1, -1, -1,
+      -2, -2, -2, -2,
+    },
+  },
+  {
+    { 2147483647 },
+    {
+                0,           0,           0,           0,
+               -1,          -1,          -1,          -1,
+      -2147483648, -2147483648, -2147483648, -2147483648,
+               -2,          -2,          -2,          -2,
+    },
+    {
+                0,           0,           0,           0,
+      -2147483647, -2147483647, -2147483647, -2147483647,
+      -2147483648, -2147483648, -2147483648, -2147483648,
+                2,           2,           2,           2,
+    },
+  },
+  {
+    { -2147483648 },
+    {
+                0,           0,           0,           0,
+                1,           1,           1,           1,
+       2147483647,  2147483647,  2147483647,  2147483647,
+                2,           2,           2,           2,
+    },
+    {
+                0,           0,           0,           0,
+      -2147483648, -2147483648, -2147483648, -2147483648,
+      -2147483648, -2147483648, -2147483648, -2147483648,
+                0,           0,           0,           0,
+    },
+  },
+};
+
+int64_t TEST_BINARY_DATA(int64_t, mul)[][3][N] =
+{
+  {
+    { 1 },
+    {
+       0,  0,  0,  0,
+       1,  1,  1,  1,
+      -1, -1, -1, -1,
+      -2, -2, -2, -2,
+    },
+    {
+       0,  0,  0,  0,
+       1,  1,  1,  1,
+      -1, -1, -1, -1,
+      -2, -2, -2, -2,
+    },
+  },
+  {
+    { 9223372036854775807ll },
+    {
+                            0,                       0,                       
0,                       0,
+                           -1,                      -1,                      
-1,                      -1,
+      -9223372036854775808ull, -9223372036854775808ull, 
-9223372036854775808ull, -9223372036854775808ull,
+                           -2,                      -2,                      
-2,                      -2,
+    },
+    {
+                            0,                       0,                       
0,                       0,
+       -9223372036854775807ll,  -9223372036854775807ll,  
-9223372036854775807ll,  -9223372036854775807ll,
+      -9223372036854775808ull, -9223372036854775808ull, 
-9223372036854775808ull, -9223372036854775808ull,
+                            2,                       2,                       
2,                       2,
+    },
+  },
+  {
+    { -9223372036854775808ull },
+    {
+                           0,                      0,                      0,  
                    0,
+                           1,                      1,                      1,  
                    1,
+       9223372036854775807ll,  9223372036854775807ll,  9223372036854775807ll,  
9223372036854775807ll,
+                           2,                      2,                      2,  
                    2,
+    },
+    {
+                            0,                       0,                       
0,                       0,
+      -9223372036854775808ull, -9223372036854775808ull, 
-9223372036854775808ull, -9223372036854775808ull,
+      -9223372036854775808ull, -9223372036854775808ull, 
-9223372036854775808ull, -9223372036854775808ull,
+                            0,                       0,                       
0,                       0,
+    },
+  },
+};
+
 #endif
diff --git 
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmul-run-1-i16.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmul-run-1-i16.c
new file mode 100644
index 00000000000..c6be0ec88db
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmul-run-1-i16.c
@@ -0,0 +1,15 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */
+
+#include "vx_binary.h"
+#include "vx_binary_data.h"
+
+#define T    int16_t
+#define NAME mul
+
+DEF_VX_BINARY_CASE_0_WRAP(T, *, NAME)
+
+#define TEST_DATA                        TEST_BINARY_DATA_WRAP(T, NAME)
+#define TEST_RUN(T, NAME, out, in, x, n) RUN_VX_BINARY_CASE_0_WRAP(T, NAME, 
out, in, x, n)
+
+#include "vx_binary_run.h"
diff --git 
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmul-run-1-i32.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmul-run-1-i32.c
new file mode 100644
index 00000000000..3c78042b0f0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmul-run-1-i32.c
@@ -0,0 +1,15 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */
+
+#include "vx_binary.h"
+#include "vx_binary_data.h"
+
+#define T    int32_t
+#define NAME mul
+
+DEF_VX_BINARY_CASE_0_WRAP(T, *, NAME)
+
+#define TEST_DATA                        TEST_BINARY_DATA_WRAP(T, NAME)
+#define TEST_RUN(T, NAME, out, in, x, n) RUN_VX_BINARY_CASE_0_WRAP(T, NAME, 
out, in, x, n)
+
+#include "vx_binary_run.h"
diff --git 
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmul-run-1-i64.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmul-run-1-i64.c
new file mode 100644
index 00000000000..63925d9307d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmul-run-1-i64.c
@@ -0,0 +1,15 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */
+
+#include "vx_binary.h"
+#include "vx_binary_data.h"
+
+#define T    int64_t
+#define NAME mul
+
+DEF_VX_BINARY_CASE_0_WRAP(T, *, NAME)
+
+#define TEST_DATA                        TEST_BINARY_DATA_WRAP(T, NAME)
+#define TEST_RUN(T, NAME, out, in, x, n) RUN_VX_BINARY_CASE_0_WRAP(T, NAME, 
out, in, x, n)
+
+#include "vx_binary_run.h"
diff --git 
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmul-run-1-i8.c 
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmul-run-1-i8.c
new file mode 100644
index 00000000000..69962f52011
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmul-run-1-i8.c
@@ -0,0 +1,15 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */
+
+#include "vx_binary.h"
+#include "vx_binary_data.h"
+
+#define T    int8_t
+#define NAME mul
+
+DEF_VX_BINARY_CASE_0_WRAP(T, *, NAME)
+
+#define TEST_DATA                        TEST_BINARY_DATA_WRAP(T, NAME)
+#define TEST_RUN(T, NAME, out, in, x, n) RUN_VX_BINARY_CASE_0_WRAP(T, NAME, 
out, in, x, n)
+
+#include "vx_binary_run.h"
-- 
2.43.0

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