On 5/21/25 12:20 PM, Shreya Munnangi wrote:
Patch is originally from Siarhei Volkau <lis8...@gmail.com
<mailto:lis8...@gmail.com>>.
RISC-V has a zero register (x0) which we can use to store zero into memory
without loading the constant into a distinct register. Adjust the
constraints
of the 32-bit movdi_32bit pattern to recognize that we can store 0.0 into
memory using x0 as the source register.
This patch only affects RISC-V. It has been regression tested on
riscv64-elf.
Jeff has also tested this in his tester (riscv64-elf and riscv32-elf)
with no
regressions.
PR target/70557
gcc/
* config/riscv/riscv.md (movdi_32bit): Add "J" constraint to
allow storing 0
directly to memory.
So you forgot to attach the patch. Usually when you do this you'll get
the response "ENOPATCH" from someone which means "error, no patch".
Can you resend with the patch attached ;-)
jeff
