From: xuli <[email protected]>
This patch adds testcase for form1, as shown below:
void __attribute__((noinline)) \
vec_sat_s_add_imm_##T##_fmt_1##_##INDEX (T *out, T *op_1, unsigned limit) \
{ \
unsigned i; \
for (i = 0; i < limit; i++) \
{ \
T x = op_1[i]; \
T sum = (UT)x + (UT)IMM; \
out[i] = (x ^ IMM) < 0 \
? sum \
: (sum ^ x) >= 0 \
? sum \
: x < 0 ? MIN : MAX; \
} \
}
Passed the rv64gcv regression test.
Signed-off-by: Li Xu <[email protected]>
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/sat/vec_sat_arith.h: add signed vec
SAT_ADD IMM form1.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_data.h: add sat_s_add_imm
data.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add_imm-1-i16.c: New test.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add_imm-1-i32.c: New test.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add_imm-1-i64.c: New test.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add_imm-1-i8.c: New test.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add_imm-run-1-i16.c: New
test.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add_imm-run-1-i32.c: New
test.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add_imm-run-1-i64.c: New
test.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add_imm-run-1-i8.c: New
test.
*
gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add_imm_type_check-1-i16.c: New test.
*
gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add_imm_type_check-1-i32.c: New test.
* gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add_imm_type_check-1-i8.c:
New test.
---
.../riscv/rvv/autovec/sat/vec_sat_arith.h | 25 ++
.../riscv/rvv/autovec/sat/vec_sat_data.h | 240 ++++++++++++++++++
.../rvv/autovec/sat/vec_sat_s_add_imm-1-i16.c | 10 +
.../rvv/autovec/sat/vec_sat_s_add_imm-1-i32.c | 10 +
.../rvv/autovec/sat/vec_sat_s_add_imm-1-i64.c | 10 +
.../rvv/autovec/sat/vec_sat_s_add_imm-1-i8.c | 10 +
.../autovec/sat/vec_sat_s_add_imm-run-1-i16.c | 28 ++
.../autovec/sat/vec_sat_s_add_imm-run-1-i32.c | 28 ++
.../autovec/sat/vec_sat_s_add_imm-run-1-i64.c | 28 ++
.../autovec/sat/vec_sat_s_add_imm-run-1-i8.c | 28 ++
.../sat/vec_sat_s_add_imm_type_check-1-i16.c | 9 +
.../sat/vec_sat_s_add_imm_type_check-1-i32.c | 9 +
.../sat/vec_sat_s_add_imm_type_check-1-i8.c | 10 +
13 files changed, 445 insertions(+)
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add_imm-1-i16.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add_imm-1-i32.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add_imm-1-i64.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add_imm-1-i8.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add_imm-run-1-i16.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add_imm-run-1-i32.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add_imm-run-1-i64.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add_imm-run-1-i8.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add_imm_type_check-1-i16.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add_imm_type_check-1-i32.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add_imm_type_check-1-i8.c
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_arith.h
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_arith.h
index 7db892cc2e9..ffdccd79b7a 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_arith.h
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_arith.h
@@ -314,6 +314,31 @@ vec_sat_s_add_##T##_fmt_4 (T *out, T *op_1, T *op_2,
unsigned limit) \
#define RUN_VEC_SAT_S_ADD_FMT_4_WRAP(T, out, op_1, op_2, N) \
RUN_VEC_SAT_S_ADD_FMT_4(T, out, op_1, op_2, N)
+#define DEF_VEC_SAT_S_ADD_IMM_FMT_1(INDEX, T, UT, IMM, MIN, MAX) \
+void __attribute__((noinline)) \
+vec_sat_s_add_imm_##T##_fmt_1##_##INDEX (T *out, T *op_1, unsigned limit) \
+{ \
+ unsigned i; \
+ for (i = 0; i < limit; i++) \
+ { \
+ T x = op_1[i]; \
+ T sum = (UT)x + (UT)IMM; \
+ out[i] = (x ^ IMM) < 0 \
+ ? sum \
+ : (sum ^ x) >= 0 \
+ ? sum \
+ : x < 0 ? MIN : MAX; \
+ } \
+}
+#define DEF_VEC_SAT_S_ADD_IMM_FMT_1_WRAP(INDEX, T, UT, IMM, MIN, MAX) \
+ DEF_VEC_SAT_S_ADD_IMM_FMT_1(INDEX, T, UT, IMM, MIN, MAX)
+
+#define RUN_VEC_SAT_S_ADD_IMM_FMT_1(INDEX, T, out, in, expect, IMM, N) \
+ vec_sat_s_add_imm_##T##_fmt_1##_##INDEX (out, in, N); \
+ VALIDATE_RESULT (out, expect, N)
+#define RUN_VEC_SAT_S_ADD_IMM_FMT_1_WRAP(INDEX, T, out, in, expect, IMM, N) \
+ RUN_VEC_SAT_S_ADD_IMM_FMT_1(INDEX, T, out, in, expect, IMM, N)
+
/******************************************************************************/
/* Saturation Sub (Unsigned and Signed)
*/
/******************************************************************************/
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_data.h
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_data.h
index ec4d64cc100..9f05c0c9291 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_data.h
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_data.h
@@ -744,6 +744,246 @@ uint64_t TEST_UNARY_DATA(uint64_t, sat_u_sub_imm)[][2][N]
=
},
};
+int8_t TEST_UNARY_DATA(int8_t, sat_s_add_imm)[][2][N] =
+{
+ { /* For add imm -128 */
+ {
+ -128, 0, 100, 127,
+ -128, 0, 100, 127,
+ -128, 0, 100, 127,
+ -128, 0, 100, 127,
+ },
+ {
+ -128, -128, -28, -1,
+ -128, -128, -28, -1,
+ -128, -128, -28, -1,
+ -128, -128, -28, -1,
+ },
+ },
+ { /* For add imm 0 */
+ {
+ -128, 0, 100, 127,
+ -128, 0, 100, 127,
+ -128, 0, 100, 127,
+ -128, 0, 100, 127,
+ },
+ {
+ -128, 0, 100, 127,
+ -128, 0, 100, 127,
+ -128, 0, 100, 127,
+ -128, 0, 100, 127,
+ },
+ },
+ { /* For add imm 1 */
+ {
+ -128, 0, 100, 127,
+ -128, 0, 100, 127,
+ -128, 0, 100, 127,
+ -128, 0, 100, 127,
+ },
+ {
+ -127, 1, 101, 127,
+ -127, 1, 101, 127,
+ -127, 1, 101, 127,
+ -127, 1, 101, 127,
+ },
+ },
+ { /* For add imm 127 */
+ {
+ -128, 0, 100, 127,
+ -128, 0, 100, 127,
+ -128, 0, 100, 127,
+ -128, 0, 100, 127,
+ },
+ {
+ -1, 127, 127, 127,
+ -1, 127, 127, 127,
+ -1, 127, 127, 127,
+ -1, 127, 127, 127,
+ },
+ },
+};
+
+int16_t TEST_UNARY_DATA(int16_t, sat_s_add_imm)[][2][N] =
+{
+ { /* For add imm -32768 */
+ {
+ -32768, 0, 100, 32767,
+ -32768, 0, 100, 32767,
+ -32768, 0, 100, 32767,
+ -32768, 0, 100, 32767,
+ },
+ {
+ -32768, -32768, -32668, -1,
+ -32768, -32768, -32668, -1,
+ -32768, -32768, -32668, -1,
+ -32768, -32768, -32668, -1,
+ },
+ },
+ { /* For add imm 0 */
+ {
+ -32768, 0, 100, 32767,
+ -32768, 0, 100, 32767,
+ -32768, 0, 100, 32767,
+ -32768, 0, 100, 32767,
+ },
+ {
+ -32768, 0, 100, 32767,
+ -32768, 0, 100, 32767,
+ -32768, 0, 100, 32767,
+ -32768, 0, 100, 32767,
+ },
+ },
+ { /* For add imm 1 */
+ {
+ -32768, 0, 100, 32767,
+ -32768, 0, 100, 32767,
+ -32768, 0, 100, 32767,
+ -32768, 0, 100, 32767,
+ },
+ {
+ -32767, 1, 101, 32767,
+ -32767, 1, 101, 32767,
+ -32767, 1, 101, 32767,
+ -32767, 1, 101, 32767,
+ },
+ },
+ { /* For add imm 32767 */
+ {
+ -32768, 0, 100, 32767,
+ -32768, 0, 100, 32767,
+ -32768, 0, 100, 32767,
+ -32768, 0, 100, 32767,
+ },
+ {
+ -1, 32767, 32767, 32767,
+ -1, 32767, 32767, 32767,
+ -1, 32767, 32767, 32767,
+ -1, 32767, 32767, 32767,
+ },
+ },
+};
+
+int32_t TEST_UNARY_DATA(int32_t, sat_s_add_imm)[][2][N] =
+{
+ { /* For add imm -2147483648 */
+ {
+ -2147483648, 0, 100, 2147483647,
+ -2147483648, 0, 100, 2147483647,
+ -2147483648, 0, 100, 2147483647,
+ -2147483648, 0, 100, 2147483647,
+ },
+ {
+ -2147483648, -2147483648, -2147483548, -1,
+ -2147483648, -2147483648, -2147483548, -1,
+ -2147483648, -2147483648, -2147483548, -1,
+ -2147483648, -2147483648, -2147483548, -1,
+ },
+ },
+ { /* For add imm 0 */
+ {
+ -2147483648, 0, 100, 2147483647,
+ -2147483648, 0, 100, 2147483647,
+ -2147483648, 0, 100, 2147483647,
+ -2147483648, 0, 100, 2147483647,
+ },
+ {
+ -2147483648, 0, 100, 2147483647,
+ -2147483648, 0, 100, 2147483647,
+ -2147483648, 0, 100, 2147483647,
+ -2147483648, 0, 100, 2147483647,
+ },
+ },
+ { /* For add imm 1 */
+ {
+ -2147483648, 0, 100, 2147483647,
+ -2147483648, 0, 100, 2147483647,
+ -2147483648, 0, 100, 2147483647,
+ -2147483648, 0, 100, 2147483647,
+ },
+ {
+ -2147483647, 1, 101, 2147483647,
+ -2147483647, 1, 101, 2147483647,
+ -2147483647, 1, 101, 2147483647,
+ -2147483647, 1, 101, 2147483647,
+ },
+ },
+ { /* For add imm 2147483647 */
+ {
+ -2147483648, 0, 100, 2147483647,
+ -2147483648, 0, 100, 2147483647,
+ -2147483648, 0, 100, 2147483647,
+ -2147483648, 0, 100, 2147483647,
+ },
+ {
+ -1, 2147483647, 2147483647, 2147483647,
+ -1, 2147483647, 2147483647, 2147483647,
+ -1, 2147483647, 2147483647, 2147483647,
+ -1, 2147483647, 2147483647, 2147483647,
+ },
+ },
+};
+
+int64_t TEST_UNARY_DATA(int64_t, sat_s_add_imm)[][2][N] =
+{
+ { /* For add imm -9223372036854775808ll */
+ {
+ INT64_MIN, 0, 100, INT64_MAX,
+ INT64_MIN, 0, 100, INT64_MAX,
+ INT64_MIN, 0, 100, INT64_MAX,
+ INT64_MIN, 0, 100, INT64_MAX,
+ },
+ {
+ INT64_MIN, INT64_MIN, -9223372036854775708ll, -1,
+ INT64_MIN, INT64_MIN, -9223372036854775708ll, -1,
+ INT64_MIN, INT64_MIN, -9223372036854775708ll, -1,
+ INT64_MIN, INT64_MIN, -9223372036854775708ll, -1,
+ },
+ },
+ { /* For add imm 0 */
+ {
+ INT64_MIN, 0, 100, INT64_MAX,
+ INT64_MIN, 0, 100, INT64_MAX,
+ INT64_MIN, 0, 100, INT64_MAX,
+ INT64_MIN, 0, 100, INT64_MAX,
+ },
+ {
+ INT64_MIN, 0, 100, INT64_MAX,
+ INT64_MIN, 0, 100, INT64_MAX,
+ INT64_MIN, 0, 100, INT64_MAX,
+ INT64_MIN, 0, 100, INT64_MAX,
+ },
+ },
+ { /* For add imm 1 */
+ {
+ INT64_MIN, 0, 100, INT64_MAX,
+ INT64_MIN, 0, 100, INT64_MAX,
+ INT64_MIN, 0, 100, INT64_MAX,
+ INT64_MIN, 0, 100, INT64_MAX,
+ },
+ {
+ -INT64_MAX, 1, 101, INT64_MAX,
+ -INT64_MAX, 1, 101, INT64_MAX,
+ -INT64_MAX, 1, 101, INT64_MAX,
+ -INT64_MAX, 1, 101, INT64_MAX,
+ },
+ },
+ { /* For add imm 9223372036854775807ll */
+ {
+ INT64_MIN, 0, 100, INT64_MAX,
+ INT64_MIN, 0, 100, INT64_MAX,
+ INT64_MIN, 0, 100, INT64_MAX,
+ INT64_MIN, 0, 100, INT64_MAX,
+ },
+ {
+ -1, INT64_MAX, INT64_MAX, INT64_MAX,
+ -1, INT64_MAX, INT64_MAX, INT64_MAX,
+ -1, INT64_MAX, INT64_MAX, INT64_MAX,
+ -1, INT64_MAX, INT64_MAX, INT64_MAX,
+ },
+ },
+};
+
#define TEST_BINARY_DATA_NAME(T1, T2, NAME)
test_bin_##T1##_##T2##_##NAME##_data
#define TEST_BINARY_DATA_NAME_WRAP(T1, T2, NAME) \
TEST_BINARY_DATA_NAME(T1, T2, NAME)
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add_imm-1-i16.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add_imm-1-i16.c
new file mode 100644
index 00000000000..396c741d321
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add_imm-1-i16.c
@@ -0,0 +1,10 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-tree-optimized" } */
+
+#include "vec_sat_arith.h"
+
+DEF_VEC_SAT_S_ADD_IMM_FMT_1(0, int16_t, uint16_t, 9, INT16_MIN, INT16_MAX)
+
+/* { dg-final { scan-tree-dump-times ".SAT_ADD " 1 "optimized" { target {
no-opts "-O2" } } } } */
+/* { dg-final { scan-tree-dump-times ".SAT_ADD " 2 "optimized" { target {
no-opts "-O3" } } } } */
+/* { dg-final { scan-assembler-times {vsadd\.vi} 1 } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add_imm-1-i32.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add_imm-1-i32.c
new file mode 100644
index 00000000000..da9e53879d1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add_imm-1-i32.c
@@ -0,0 +1,10 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-tree-optimized" } */
+
+#include "vec_sat_arith.h"
+
+DEF_VEC_SAT_S_ADD_IMM_FMT_1(0, int32_t, uint32_t, 9, INT32_MIN, INT32_MAX)
+
+/* { dg-final { scan-tree-dump-times ".SAT_ADD " 1 "optimized" { target {
no-opts "-O2" } } } } */
+/* { dg-final { scan-tree-dump-times ".SAT_ADD " 2 "optimized" { target {
no-opts "-O3" } } } } */
+/* { dg-final { scan-assembler-times {vsadd\.vi} 1 } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add_imm-1-i64.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add_imm-1-i64.c
new file mode 100644
index 00000000000..e9af1a159df
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add_imm-1-i64.c
@@ -0,0 +1,10 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-tree-optimized" } */
+
+#include "vec_sat_arith.h"
+
+DEF_VEC_SAT_S_ADD_IMM_FMT_1(0, int64_t, uint64_t, 9, INT64_MIN, INT64_MAX)
+
+/* { dg-final { scan-tree-dump-times ".SAT_ADD " 1 "optimized" { target {
no-opts "-O2" } } } } */
+/* { dg-final { scan-tree-dump-times ".SAT_ADD " 2 "optimized" { target {
no-opts "-O3" } } } } */
+/* { dg-final { scan-assembler-times {vsadd\.vi} 1 } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add_imm-1-i8.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add_imm-1-i8.c
new file mode 100644
index 00000000000..66b9d7f4a2d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add_imm-1-i8.c
@@ -0,0 +1,10 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-tree-optimized" } */
+
+#include "vec_sat_arith.h"
+
+DEF_VEC_SAT_S_ADD_IMM_FMT_1(0, int8_t, uint8_t, 9, INT8_MIN, INT8_MAX)
+
+/* { dg-final { scan-tree-dump-times ".SAT_ADD " 1 "optimized" { target {
no-opts "-O2" } } } } */
+/* { dg-final { scan-tree-dump-times ".SAT_ADD " 2 "optimized" { target {
no-opts "-O3" } } } } */
+/* { dg-final { scan-assembler-times {vsadd\.vi} 1 } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add_imm-run-1-i16.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add_imm-run-1-i16.c
new file mode 100644
index 00000000000..fbfa4e23bff
--- /dev/null
+++
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add_imm-run-1-i16.c
@@ -0,0 +1,28 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99" } */
+
+#include "vec_sat_arith.h"
+#include "vec_sat_data.h"
+
+#define T int16_t
+#define RUN(INDEX, T, out, in, expect, IMM, N) \
+ RUN_VEC_SAT_S_ADD_IMM_FMT_1_WRAP (INDEX, T, out, in, expect, IMM, N)
+
+DEF_VEC_SAT_S_ADD_IMM_FMT_1_WRAP(0, int16_t, uint16_t, -32768, INT16_MIN,
INT16_MAX)
+DEF_VEC_SAT_S_ADD_IMM_FMT_1_WRAP(1, int16_t, uint16_t, 0, INT16_MIN, INT16_MAX)
+DEF_VEC_SAT_S_ADD_IMM_FMT_1_WRAP(2, int16_t, uint16_t, 1, INT16_MIN, INT16_MAX)
+DEF_VEC_SAT_S_ADD_IMM_FMT_1_WRAP(3, int16_t, uint16_t, 32767, INT16_MIN,
INT16_MAX)
+
+int
+main ()
+{
+ T out[N];
+ T (*d)[2][N] = TEST_UNARY_DATA_WRAP (T, sat_s_add_imm);
+
+ RUN (0, T, out, d[0][0], d[0][1], -32768, N);
+ RUN (1, T, out, d[1][0], d[1][1], 0, N);
+ RUN (2, T, out, d[2][0], d[2][1], 1, N);
+ RUN (3, T, out, d[3][0], d[3][1], 32767, N);
+
+ return 0;
+}
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add_imm-run-1-i32.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add_imm-run-1-i32.c
new file mode 100644
index 00000000000..5f1763cb060
--- /dev/null
+++
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add_imm-run-1-i32.c
@@ -0,0 +1,28 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99" } */
+
+#include "vec_sat_arith.h"
+#include "vec_sat_data.h"
+
+#define T int32_t
+#define RUN(INDEX, T, out, in, expect, IMM, N) \
+ RUN_VEC_SAT_S_ADD_IMM_FMT_1_WRAP (INDEX, T, out, in, expect, IMM, N)
+
+DEF_VEC_SAT_S_ADD_IMM_FMT_1_WRAP(0, int32_t, uint32_t, -2147483648, INT32_MIN,
INT32_MAX)
+DEF_VEC_SAT_S_ADD_IMM_FMT_1_WRAP(1, int32_t, uint32_t, 0, INT32_MIN, INT32_MAX)
+DEF_VEC_SAT_S_ADD_IMM_FMT_1_WRAP(2, int32_t, uint32_t, 1, INT32_MIN, INT32_MAX)
+DEF_VEC_SAT_S_ADD_IMM_FMT_1_WRAP(3, int32_t, uint32_t, 2147483647, INT32_MIN,
INT32_MAX)
+
+int
+main ()
+{
+ T out[N];
+ T (*d)[2][N] = TEST_UNARY_DATA_WRAP (T, sat_s_add_imm);
+
+ RUN (0, T, out, d[0][0], d[0][1], -2147483648, N);
+ RUN (1, T, out, d[1][0], d[1][1], 0, N);
+ RUN (2, T, out, d[2][0], d[2][1], 1, N);
+ RUN (3, T, out, d[3][0], d[3][1], 2147483647, N);
+
+ return 0;
+}
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add_imm-run-1-i64.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add_imm-run-1-i64.c
new file mode 100644
index 00000000000..435eb1bcdc4
--- /dev/null
+++
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add_imm-run-1-i64.c
@@ -0,0 +1,28 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99" } */
+
+#include "vec_sat_arith.h"
+#include "vec_sat_data.h"
+
+#define T int64_t
+#define RUN(INDEX, T, out, in, expect, IMM, N) \
+ RUN_VEC_SAT_S_ADD_IMM_FMT_1_WRAP (INDEX, T, out, in, expect, IMM, N)
+
+DEF_VEC_SAT_S_ADD_IMM_FMT_1_WRAP(0, int64_t, uint64_t, INT64_MIN, INT64_MIN,
INT64_MAX)
+DEF_VEC_SAT_S_ADD_IMM_FMT_1_WRAP(1, int64_t, uint64_t, 0, INT64_MIN, INT64_MAX)
+DEF_VEC_SAT_S_ADD_IMM_FMT_1_WRAP(2, int64_t, uint64_t, 1, INT64_MIN, INT64_MAX)
+DEF_VEC_SAT_S_ADD_IMM_FMT_1_WRAP(3, int64_t, uint64_t, INT64_MAX, INT64_MIN,
INT64_MAX)
+
+int
+main ()
+{
+ T out[N];
+ T (*d)[2][N] = TEST_UNARY_DATA_WRAP (T, sat_s_add_imm);
+
+ RUN (0, T, out, d[0][0], d[0][1], INT64_MIN, N);
+ RUN (1, T, out, d[1][0], d[1][1], 0, N);
+ RUN (2, T, out, d[2][0], d[2][1], 1, N);
+ RUN (3, T, out, d[3][0], d[3][1], INT64_MAX, N);
+
+ return 0;
+}
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add_imm-run-1-i8.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add_imm-run-1-i8.c
new file mode 100644
index 00000000000..535e873fe9a
--- /dev/null
+++
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add_imm-run-1-i8.c
@@ -0,0 +1,28 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-additional-options "-std=c99" } */
+
+#include "vec_sat_arith.h"
+#include "vec_sat_data.h"
+
+#define T int8_t
+#define RUN(INDEX, T, out, in, expect, IMM, N) \
+ RUN_VEC_SAT_S_ADD_IMM_FMT_1_WRAP (INDEX, T, out, in, expect, IMM, N)
+
+DEF_VEC_SAT_S_ADD_IMM_FMT_1_WRAP(0, int8_t, uint8_t, -128, INT8_MIN, INT8_MAX)
+DEF_VEC_SAT_S_ADD_IMM_FMT_1_WRAP(1, int8_t, uint8_t, 0, INT8_MIN, INT8_MAX)
+DEF_VEC_SAT_S_ADD_IMM_FMT_1_WRAP(2, int8_t, uint8_t, 1, INT8_MIN, INT8_MAX)
+DEF_VEC_SAT_S_ADD_IMM_FMT_1_WRAP(3, int8_t, uint8_t, 127, INT8_MIN, INT8_MAX)
+
+int
+main ()
+{
+ T out[N];
+ T (*d)[2][N] = TEST_UNARY_DATA_WRAP (T, sat_s_add_imm);
+
+ RUN (0, T, out, d[0][0], d[0][1], -128, N);
+ RUN (1, T, out, d[1][0], d[1][1], 0, N);
+ RUN (2, T, out, d[2][0], d[2][1], 1, N);
+ RUN (3, T, out, d[3][0], d[3][1], 127, N);
+
+ return 0;
+}
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add_imm_type_check-1-i16.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add_imm_type_check-1-i16.c
new file mode 100644
index 00000000000..26e96fc18f0
--- /dev/null
+++
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add_imm_type_check-1-i16.c
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */
+
+#include "vec_sat_arith.h"
+
+DEF_VEC_SAT_S_ADD_IMM_FMT_1(0, int16_t, uint16_t, -32769, INT16_MIN, INT16_MAX)
+DEF_VEC_SAT_S_ADD_IMM_FMT_1(1, int16_t, uint16_t, 32768, INT16_MIN, INT16_MAX)
+
+/* { dg-final { scan-tree-dump-not ".SAT_ADD " "optimized" } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add_imm_type_check-1-i32.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add_imm_type_check-1-i32.c
new file mode 100644
index 00000000000..519e72c7b8c
--- /dev/null
+++
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add_imm_type_check-1-i32.c
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -fdump-tree-optimized" } */
+
+#include "vec_sat_arith.h"
+
+DEF_VEC_SAT_S_ADD_IMM_FMT_1(0, int32_t, uint32_t, -2147483649, INT32_MIN,
INT32_MAX)
+DEF_VEC_SAT_S_ADD_IMM_FMT_1(1, int32_t, uint32_t, 2147483648, INT32_MIN,
INT32_MAX)
+
+/* { dg-final { scan-tree-dump-not ".SAT_ADD " "optimized" } } */
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add_imm_type_check-1-i8.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add_imm_type_check-1-i8.c
new file mode 100644
index 00000000000..2b0af52ee07
--- /dev/null
+++
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/sat/vec_sat_s_add_imm_type_check-1-i8.c
@@ -0,0 +1,10 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -ftree-vectorize
-fdump-tree-optimized" } */
+
+#include "vec_sat_arith.h"
+
+DEF_VEC_SAT_S_ADD_IMM_FMT_1(0, int8_t, uint8_t, 200, INT8_MIN, INT8_MAX)
+DEF_VEC_SAT_S_ADD_IMM_FMT_1(1, int8_t, uint8_t, -300, INT8_MIN, INT8_MAX)
+
+/* { dg-final { scan-tree-dump-not ".SAT_ADD " "optimized" } } */
+
--
2.17.1
