[PATCH v2 0/1]RISC-V :The following changes enable P8700 MIPS processor for RISC-V.

[Umesh Kalappa]

>>Every type listed in that attribute must have a mapping to a function unit in 
>>your scheduler model
Thank you Jeff and added the dummies reservation for the leftout attributes and 
tested with dejagnu riscv.exp.

Thank you again for reference
~U