From: Pan Li <pan2...@intel.com>
This patch would like to introduce the combine of vec_dup + vsub.vv into
vsub.vx on the cost value of GR2VR. The late-combine will take place if
the cost of GR2VR is zero, or reject the combine if non-zero like 1, 15
in test. There will be two cases for the combine:
Case 0:
| ...
| vmv.v.x
| L1:
| vsub.vv
| J L1
| ...
Case 1:
| ...
| L1:
| vmv.v.x
| vsub.vv
| J L1
| ...
Both will be combined to below if the cost of GR2VR is zero.
| ...
| L1:
| vsub.vx
| J L1
| ...
The below test suites are passed for this patch series.
* The rv64gcv fully regression test.
Pan Li (10):
RISC-V: Combine vec_duplicate + vsub.vv to vsub.vx on GR2VR cost
RISC-V: Rename vx_vadd-* testcase to vx-* for all vx combine [NFC]
RISC-V: Adjust vx combine test case to avoid name conflict
RISC-V: Add test for vec_duplicate + vsub.vv combine case 0 with GR2VR cost 0
RISC-V: Add test for vec_duplicate + vsub.vv combine case 0 with GR2VR cost 1
RISC-V: Add test for vec_duplicate + vsub.vv combine case 0 with GR2VR cost 15
RISC-V: Add test for vec_duplicate + vsub.vv combine case 1 with GR2VR cost 0
RISC-V: Add test for vec_duplicate + vsub.vv combine case 1 with GR2VR cost 1
RISC-V: Add test for vec_duplicate + vsub.vv combine case 1 with GR2VR cost 2
RISC-V: Reuse test name for vx combine test data [NFC]
gcc/config/riscv/autovec-opt.md | 17 +
gcc/config/riscv/riscv.cc | 1 +
gcc/config/riscv/vector-iterators.md | 2 +-
.../vx_vf/{vx_vadd-1-i32.c => vx-1-i16.c} | 4 +-
.../vx_vf/{vx_vadd-1-i64.c => vx-1-i32.c} | 4 +-
.../vx_vf/{vx_vadd-1-i8.c => vx-1-i64.c} | 4 +-
.../vx_vf/{vx_vadd-1-i16.c => vx-1-i8.c} | 4 +-
.../riscv/rvv/autovec/vx_vf/vx-1-u16.c | 10 +
.../riscv/rvv/autovec/vx_vf/vx-1-u32.c | 10 +
.../riscv/rvv/autovec/vx_vf/vx-1-u64.c | 10 +
.../riscv/rvv/autovec/vx_vf/vx-1-u8.c | 10 +
.../vx_vf/{vx_vadd-2-i32.c => vx-2-i16.c} | 4 +-
.../vx_vf/{vx_vadd-2-i64.c => vx-2-i32.c} | 4 +-
.../vx_vf/{vx_vadd-2-i8.c => vx-2-i64.c} | 4 +-
.../vx_vf/{vx_vadd-2-i16.c => vx-2-i8.c} | 4 +-
.../riscv/rvv/autovec/vx_vf/vx-2-u16.c | 10 +
.../riscv/rvv/autovec/vx_vf/vx-2-u32.c | 10 +
.../riscv/rvv/autovec/vx_vf/vx-2-u64.c | 10 +
.../riscv/rvv/autovec/vx_vf/vx-2-u8.c | 10 +
.../vx_vf/{vx_vadd-3-i32.c => vx-3-i16.c} | 4 +-
.../vx_vf/{vx_vadd-3-i64.c => vx-3-i32.c} | 4 +-
.../vx_vf/{vx_vadd-3-i8.c => vx-3-i64.c} | 4 +-
.../vx_vf/{vx_vadd-3-i16.c => vx-3-i8.c} | 4 +-
.../riscv/rvv/autovec/vx_vf/vx-3-u16.c | 10 +
.../riscv/rvv/autovec/vx_vf/vx-3-u32.c | 10 +
.../riscv/rvv/autovec/vx_vf/vx-3-u64.c | 10 +
.../riscv/rvv/autovec/vx_vf/vx-3-u8.c | 10 +
.../riscv/rvv/autovec/vx_vf/vx-4-i16.c | 10 +
.../vx_vf/{vx_vadd-4-i64.c => vx-4-i32.c} | 4 +-
.../vx_vf/{vx_vadd-4-i16.c => vx-4-i64.c} | 4 +-
.../vx_vf/{vx_vadd-4-i8.c => vx-4-i8.c} | 4 +-
.../riscv/rvv/autovec/vx_vf/vx-4-u16.c | 10 +
.../riscv/rvv/autovec/vx_vf/vx-4-u32.c | 10 +
.../vx_vf/{vx_vadd-4-i32.c => vx-4-u64.c} | 4 +-
.../riscv/rvv/autovec/vx_vf/vx-4-u8.c | 10 +
.../vx_vf/{vx_vadd-5-i16.c => vx-5-i16.c} | 4 +-
.../vx_vf/{vx_vadd-5-u16.c => vx-5-i32.c} | 4 +-
.../vx_vf/{vx_vadd-5-i32.c => vx-5-i64.c} | 4 +-
.../vx_vf/{vx_vadd-5-i8.c => vx-5-i8.c} | 4 +-
.../vx_vf/{vx_vadd-5-u32.c => vx-5-u16.c} | 4 +-
.../riscv/rvv/autovec/vx_vf/vx-5-u32.c | 10 +
.../vx_vf/{vx_vadd-5-i64.c => vx-5-u64.c} | 4 +-
.../riscv/rvv/autovec/vx_vf/vx-5-u8.c | 10 +
.../vx_vf/{vx_vadd-6-u64.c => vx-6-i16.c} | 4 +-
.../vx_vf/{vx_vadd-6-i32.c => vx-6-i32.c} | 4 +-
.../vx_vf/{vx_vadd-6-i8.c => vx-6-i64.c} | 4 +-
.../vx_vf/{vx_vadd-6-i16.c => vx-6-i8.c} | 4 +-
.../vx_vf/{vx_vadd-6-u16.c => vx-6-u16.c} | 4 +-
.../vx_vf/{vx_vadd-6-u32.c => vx-6-u32.c} | 4 +-
.../vx_vf/{vx_vadd-6-i64.c => vx-6-u64.c} | 4 +-
.../vx_vf/{vx_vadd-6-u8.c => vx-6-u8.c} | 4 +-
.../riscv/rvv/autovec/vx_vf/vx_binary.h | 50 ++-
.../riscv/rvv/autovec/vx_vf/vx_binary_data.h | 408 +++++++++++++++++-
.../riscv/rvv/autovec/vx_vf/vx_binary_run.h | 2 +-
.../riscv/rvv/autovec/vx_vf/vx_vadd-1-u16.c | 8 -
.../riscv/rvv/autovec/vx_vf/vx_vadd-1-u32.c | 8 -
.../riscv/rvv/autovec/vx_vf/vx_vadd-1-u64.c | 8 -
.../riscv/rvv/autovec/vx_vf/vx_vadd-1-u8.c | 8 -
.../riscv/rvv/autovec/vx_vf/vx_vadd-2-u16.c | 8 -
.../riscv/rvv/autovec/vx_vf/vx_vadd-2-u32.c | 8 -
.../riscv/rvv/autovec/vx_vf/vx_vadd-2-u64.c | 8 -
.../riscv/rvv/autovec/vx_vf/vx_vadd-2-u8.c | 8 -
.../riscv/rvv/autovec/vx_vf/vx_vadd-3-u16.c | 8 -
.../riscv/rvv/autovec/vx_vf/vx_vadd-3-u32.c | 8 -
.../riscv/rvv/autovec/vx_vf/vx_vadd-3-u64.c | 8 -
.../riscv/rvv/autovec/vx_vf/vx_vadd-3-u8.c | 8 -
.../riscv/rvv/autovec/vx_vf/vx_vadd-4-u16.c | 8 -
.../riscv/rvv/autovec/vx_vf/vx_vadd-4-u32.c | 8 -
.../riscv/rvv/autovec/vx_vf/vx_vadd-4-u64.c | 8 -
.../riscv/rvv/autovec/vx_vf/vx_vadd-4-u8.c | 8 -
.../riscv/rvv/autovec/vx_vf/vx_vadd-5-u64.c | 8 -
.../riscv/rvv/autovec/vx_vf/vx_vadd-5-u8.c | 8 -
.../rvv/autovec/vx_vf/vx_vadd-run-1-i16.c | 9 +-
.../rvv/autovec/vx_vf/vx_vadd-run-1-i32.c | 9 +-
.../rvv/autovec/vx_vf/vx_vadd-run-1-i64.c | 9 +-
.../rvv/autovec/vx_vf/vx_vadd-run-1-i8.c | 9 +-
.../rvv/autovec/vx_vf/vx_vadd-run-1-u16.c | 9 +-
.../rvv/autovec/vx_vf/vx_vadd-run-1-u32.c | 9 +-
.../rvv/autovec/vx_vf/vx_vadd-run-1-u64.c | 9 +-
.../rvv/autovec/vx_vf/vx_vadd-run-1-u8.c | 9 +-
.../rvv/autovec/vx_vf/vx_vsub-run-1-i16.c | 15 +
.../rvv/autovec/vx_vf/vx_vsub-run-1-i32.c | 15 +
.../rvv/autovec/vx_vf/vx_vsub-run-1-i64.c | 15 +
.../rvv/autovec/vx_vf/vx_vsub-run-1-i8.c | 15 +
.../rvv/autovec/vx_vf/vx_vsub-run-1-u16.c | 15 +
.../rvv/autovec/vx_vf/vx_vsub-run-1-u32.c | 15 +
.../rvv/autovec/vx_vf/vx_vsub-run-1-u64.c | 15 +
.../rvv/autovec/vx_vf/vx_vsub-run-1-u8.c | 15 +
88 files changed, 878 insertions(+), 238 deletions(-)
rename gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/{vx_vadd-1-i32.c =>
vx-1-i16.c} (57%)
rename gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/{vx_vadd-1-i64.c =>
vx-1-i32.c} (57%)
rename gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/{vx_vadd-1-i8.c =>
vx-1-i64.c} (57%)
rename gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/{vx_vadd-1-i16.c =>
vx-1-i8.c} (57%)
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u16.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u32.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u64.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u8.c
rename gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/{vx_vadd-2-i32.c =>
vx-2-i16.c} (57%)
rename gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/{vx_vadd-2-i64.c =>
vx-2-i32.c} (57%)
rename gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/{vx_vadd-2-i8.c =>
vx-2-i64.c} (57%)
rename gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/{vx_vadd-2-i16.c =>
vx-2-i8.c} (58%)
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u16.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u32.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u64.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u8.c
rename gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/{vx_vadd-3-i32.c =>
vx-3-i16.c} (57%)
rename gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/{vx_vadd-3-i64.c =>
vx-3-i32.c} (57%)
rename gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/{vx_vadd-3-i8.c =>
vx-3-i64.c} (57%)
rename gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/{vx_vadd-3-i16.c =>
vx-3-i8.c} (58%)
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u16.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u32.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u64.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u8.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-i16.c
rename gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/{vx_vadd-4-i64.c =>
vx-4-i32.c} (52%)
rename gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/{vx_vadd-4-i16.c =>
vx-4-i64.c} (53%)
rename gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/{vx_vadd-4-i8.c =>
vx-4-i8.c} (52%)
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-u16.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-u32.c
rename gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/{vx_vadd-4-i32.c =>
vx-4-u64.c} (52%)
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-4-u8.c
rename gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/{vx_vadd-5-i16.c =>
vx-5-i16.c} (52%)
rename gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/{vx_vadd-5-u16.c =>
vx-5-i32.c} (52%)
rename gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/{vx_vadd-5-i32.c =>
vx-5-i64.c} (53%)
rename gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/{vx_vadd-5-i8.c =>
vx-5-i8.c} (52%)
rename gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/{vx_vadd-5-u32.c =>
vx-5-u16.c} (52%)
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-u32.c
rename gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/{vx_vadd-5-i64.c =>
vx-5-u64.c} (52%)
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-5-u8.c
rename gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/{vx_vadd-6-u64.c =>
vx-6-i16.c} (52%)
rename gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/{vx_vadd-6-i32.c =>
vx-6-i32.c} (52%)
rename gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/{vx_vadd-6-i8.c =>
vx-6-i64.c} (53%)
rename gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/{vx_vadd-6-i16.c =>
vx-6-i8.c} (52%)
rename gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/{vx_vadd-6-u16.c =>
vx-6-u16.c} (52%)
rename gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/{vx_vadd-6-u32.c =>
vx-6-u32.c} (52%)
rename gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/{vx_vadd-6-i64.c =>
vx-6-u64.c} (52%)
rename gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/{vx_vadd-6-u8.c =>
vx-6-u8.c} (52%)
delete mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-1-u16.c
delete mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-1-u32.c
delete mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-1-u64.c
delete mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-1-u8.c
delete mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-2-u16.c
delete mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-2-u32.c
delete mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-2-u64.c
delete mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-2-u8.c
delete mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-3-u16.c
delete mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-3-u32.c
delete mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-3-u64.c
delete mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-3-u8.c
delete mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-4-u16.c
delete mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-4-u32.c
delete mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-4-u64.c
delete mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-4-u8.c
delete mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-5-u64.c
delete mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vadd-5-u8.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-run-1-i16.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-run-1-i32.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-run-1-i64.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-run-1-i8.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-run-1-u16.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-run-1-u32.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-run-1-u64.c
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vsub-run-1-u8.c
--
2.43.0
