Re: [PATCH 7/8] AArch64: precommit test for CMPBR instructions

Richard Earnshaw Wed, 07 May 2025 06:27:51 -0700

On 07/05/2025 13:57, Richard Sandiford wrote:

Kyrylo Tkachov <ktkac...@nvidia.com> writes:

On 7 May 2025, at 12:27, Karl Meakin <karl.mea...@arm.com> wrote:


Commit the test file `cmpbr.c` before rules for generating the new
instructions are added, so that the changes in codegen are more obvious
in the next commit.


I guess that’s an LLVM best practice.
In GCC since we have the check-function-bodies mechanism we usually prefer to 
include the relevant test together with the patch that adds the optimization.
But this is not wrong either.


gcc/testsuite/ChangeLog:

* gcc.target/aarch64/cmpbr.c: New test.
---
gcc/testsuite/gcc.target/aarch64/cmpbr.c | 1378 ++++++++++++++++++++++
1 file changed, 1378 insertions(+)
create mode 100644 gcc/testsuite/gcc.target/aarch64/cmpbr.c

diff --git a/gcc/testsuite/gcc.target/aarch64/cmpbr.c 
b/gcc/testsuite/gcc.target/aarch64/cmpbr.c
new file mode 100644
index 00000000000..728d6ead91c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/cmpbr.c
@@ -0,0 +1,1378 @@
+/* Test that the instructions added by FEAT_CMPBR are emitted */
+/* { dg-do compile } */
+/* { dg-options "-march=armv9.5-a+cmpbr -O2" } */
+/* { dg-final { check-function-bodies "**" "" "" } } */


As you’ll be adding new instructions to the compiler it’d be good to have it a 
dg-do assemble test where possible.


Agreed FWIW, but:

For that you’ll need to create a new aarch64_asm_cmpbr_ok target and use it 
like so to fallback to dg-do compile when the assembler is too old:
/* { dg-do compile { target aarch64_asm_cmpbr_ok } } */


...dg-do assemble for this one :)


I don't think that works. If the first dg-do fails the test is just skipped.

You need to replicate the test with separate dg-do directives, IIRC.

R.


Thanks,
Richard

/* { dg-do compile { target { ! aarch64_asm_cmpbr_ok } } } */
Look in lib/target-supports.exp for “aarch64_asm” for how to define it.

Ok otherwise.
Thanks,
Kyrill

+
+#include <stdint.h>
+
+typedef uint8_t u8;
+typedef int8_t i8;
+
+typedef uint16_t u16;
+typedef int16_t i16;
+
+typedef uint32_t u32;
+typedef int32_t i32;
+
+typedef uint64_t u64;
+typedef int64_t i64;
+
+int taken();
+int not_taken();
+
+#define COMPARE(ty, name, op, rhs)                                             
\
+  int ty##_x0_##name##_##rhs(ty x0, ty x1) {                                   
\
+    return (x0 op rhs) ? taken() : not_taken();                                
\
+  }
+
+#define COMPARE_ALL(unsigned_ty, signed_ty, rhs)                               
\
+  COMPARE(unsigned_ty, eq, ==, rhs);                                           
\
+  COMPARE(unsigned_ty, ne, !=, rhs);                                           
\
+                                                                               
\
+  COMPARE(unsigned_ty, ult, <, rhs);                                           
\
+  COMPARE(unsigned_ty, ule, <=, rhs);                                          
\
+  COMPARE(unsigned_ty, ugt, >, rhs);                                           
\
+  COMPARE(unsigned_ty, uge, >=, rhs);                                          
\
+                                                                               
\
+  COMPARE(signed_ty, slt, <, rhs);                                             
\
+  COMPARE(signed_ty, sle, <=, rhs);                                            
\
+  COMPARE(signed_ty, sgt, >, rhs);                                             
\
+  COMPARE(signed_ty, sge, >=, rhs);
+
+// ==== CBB<cc> (register) ====
+COMPARE_ALL(u8, i8, x1);
+
+// ==== CBH<cc> (register) ====
+COMPARE_ALL(u16, i16, x1);
+
+// ==== CB<cc> (register) ====
+COMPARE_ALL(u32, i32, x1);
+COMPARE_ALL(u64, i64, x1);
+
+// ==== CB<cc> (immediate) ====
+COMPARE_ALL(u32, i32, 42);
+COMPARE_ALL(u64, i64, 42);
+
+// ==== Special cases ====
+// CBB and CBH cannot have immediate operands. Instead we have to do a MOV+CB
+COMPARE_ALL(u8, i8, 42);
+COMPARE_ALL(u16, i16, 42);
+
+// 65 is out of the range for immediate operands (0 to 63).
+// * For 8/16-bit types, use a MOV+CB as above.
+// * For 32/64-bit types, use a CMP+B<cc> instead, because
+//   B<cc> has a longer range than CB<cc>.
+COMPARE_ALL(u8, i8, 65);
+COMPARE_ALL(u16, i16, 65);
+COMPARE_ALL(u32, i32, 65);
+COMPARE_ALL(u64, i64, 65);
+
+// Comparisons against zero can use the wzr/xzr register.
+COMPARE_ALL(u8, i8, 0);
+COMPARE_ALL(u16, i16, 0);
+COMPARE_ALL(u32, i32, 0);
+COMPARE_ALL(u64, i64, 0);
+
+/*
+** u8_x0_eq_x1:
+** and w1, w1, 255
+** cmp w1, w0, uxtb
+** beq .L4
+** b not_taken
+** b taken
+*/
+
+/*
+** u8_x0_ne_x1:
+** and w1, w1, 255
+** cmp w1, w0, uxtb
+** beq .L6
+** b taken
+** b not_taken
+*/
+
+/*
+** u8_x0_ult_x1:
+** and w1, w1, 255
+** cmp w1, w0, uxtb
+** bls .L8
+** b taken
+** b not_taken
+*/
+
+/*
+** u8_x0_ule_x1:
+** and w1, w1, 255
+** cmp w1, w0, uxtb
+** bcc .L10
+** b taken
+** b not_taken
+*/
+
+/*
+** u8_x0_ugt_x1:
+** and w1, w1, 255
+** cmp w1, w0, uxtb
+** bcs .L12
+** b taken
+** b not_taken
+*/
+
+/*
+** u8_x0_uge_x1:
+** and w1, w1, 255
+** cmp w1, w0, uxtb
+** bhi .L14
+** b taken
+** b not_taken
+*/
+
+/*
+** i8_x0_slt_x1:
+** sxtb w1, w1
+** cmp w1, w0, sxtb
+** ble .L16
+** b taken
+** b not_taken
+*/
+
+/*
+** i8_x0_sle_x1:
+** sxtb w1, w1
+** cmp w1, w0, sxtb
+** blt .L18
+** b taken
+** b not_taken
+*/
+
+/*
+** i8_x0_sgt_x1:
+** sxtb w1, w1
+** cmp w1, w0, sxtb
+** bge .L20
+** b taken
+** b not_taken
+*/
+
+/*
+** i8_x0_sge_x1:
+** sxtb w1, w1
+** cmp w1, w0, sxtb
+** bgt .L22
+** b taken
+** b not_taken
+*/
+
+/*
+** u16_x0_eq_x1:
+** and w1, w1, 65535
+** cmp w1, w0, uxth
+** beq .L25
+** b not_taken
+** b taken
+*/
+
+/*
+** u16_x0_ne_x1:
+** and w1, w1, 65535
+** cmp w1, w0, uxth
+** beq .L27
+** b taken
+** b not_taken
+*/
+
+/*
+** u16_x0_ult_x1:
+** and w1, w1, 65535
+** cmp w1, w0, uxth
+** bls .L29
+** b taken
+** b not_taken
+*/
+
+/*
+** u16_x0_ule_x1:
+** and w1, w1, 65535
+** cmp w1, w0, uxth
+** bcc .L31
+** b taken
+** b not_taken
+*/
+
+/*
+** u16_x0_ugt_x1:
+** and w1, w1, 65535
+** cmp w1, w0, uxth
+** bcs .L33
+** b taken
+** b not_taken
+*/
+
+/*
+** u16_x0_uge_x1:
+** and w1, w1, 65535
+** cmp w1, w0, uxth
+** bhi .L35
+** b taken
+** b not_taken
+*/
+
+/*
+** i16_x0_slt_x1:
+** sxth w1, w1
+** cmp w1, w0, sxth
+** ble .L37
+** b taken
+** b not_taken
+*/
+
+/*
+** i16_x0_sle_x1:
+** sxth w1, w1
+** cmp w1, w0, sxth
+** blt .L39
+** b taken
+** b not_taken
+*/
+
+/*
+** i16_x0_sgt_x1:
+** sxth w1, w1
+** cmp w1, w0, sxth
+** bge .L41
+** b taken
+** b not_taken
+*/
+
+/*
+** i16_x0_sge_x1:
+** sxth w1, w1
+** cmp w1, w0, sxth
+** bgt .L43
+** b taken
+** b not_taken
+*/
+
+/*
+** u32_x0_eq_x1:
+** cmp w0, w1
+** beq .L46
+** b not_taken
+** b taken
+*/
+
+/*
+** u32_x0_ne_x1:
+** cmp w0, w1
+** beq .L48
+** b taken
+** b not_taken
+*/
+
+/*
+** u32_x0_ult_x1:
+** cmp w0, w1
+** bcs .L50
+** b taken
+** b not_taken
+*/
+
+/*
+** u32_x0_ule_x1:
+** cmp w0, w1
+** bhi .L52
+** b taken
+** b not_taken
+*/
+
+/*
+** u32_x0_ugt_x1:
+** cmp w0, w1
+** bls .L54
+** b taken
+** b not_taken
+*/
+
+/*
+** u32_x0_uge_x1:
+** cmp w0, w1
+** bcc .L56
+** b taken
+** b not_taken
+*/
+
+/*
+** i32_x0_slt_x1:
+** cmp w0, w1
+** bge .L58
+** b taken
+** b not_taken
+*/
+
+/*
+** i32_x0_sle_x1:
+** cmp w0, w1
+** bgt .L60
+** b taken
+** b not_taken
+*/
+
+/*
+** i32_x0_sgt_x1:
+** cmp w0, w1
+** ble .L62
+** b taken
+** b not_taken
+*/
+
+/*
+** i32_x0_sge_x1:
+** cmp w0, w1
+** blt .L64
+** b taken
+** b not_taken
+*/
+
+/*
+** u64_x0_eq_x1:
+** cmp x0, x1
+** beq .L67
+** b not_taken
+** b taken
+*/
+
+/*
+** u64_x0_ne_x1:
+** cmp x0, x1
+** beq .L69
+** b taken
+** b not_taken
+*/
+
+/*
+** u64_x0_ult_x1:
+** cmp x0, x1
+** bcs .L71
+** b taken
+** b not_taken
+*/
+
+/*
+** u64_x0_ule_x1:
+** cmp x0, x1
+** bhi .L73
+** b taken
+** b not_taken
+*/
+
+/*
+** u64_x0_ugt_x1:
+** cmp x0, x1
+** bls .L75
+** b taken
+** b not_taken
+*/
+
+/*
+** u64_x0_uge_x1:
+** cmp x0, x1
+** bcc .L77
+** b taken
+** b not_taken
+*/
+
+/*
+** i64_x0_slt_x1:
+** cmp x0, x1
+** bge .L79
+** b taken
+** b not_taken
+*/
+
+/*
+** i64_x0_sle_x1:
+** cmp x0, x1
+** bgt .L81
+** b taken
+** b not_taken
+*/
+
+/*
+** i64_x0_sgt_x1:
+** cmp x0, x1
+** ble .L83
+** b taken
+** b not_taken
+*/
+
+/*
+** i64_x0_sge_x1:
+** cmp x0, x1
+** blt .L85
+** b taken
+** b not_taken
+*/
+
+/*
+** u32_x0_eq_42:
+** cmp w0, 42
+** beq .L88
+** b not_taken
+** b taken
+*/
+
+/*
+** u32_x0_ne_42:
+** cmp w0, 42
+** beq .L90
+** b taken
+** b not_taken
+*/
+
+/*
+** u32_x0_ult_42:
+** cmp w0, 41
+** bhi .L92
+** b taken
+** b not_taken
+*/
+
+/*
+** u32_x0_ule_42:
+** cmp w0, 42
+** bhi .L94
+** b taken
+** b not_taken
+*/
+
+/*
+** u32_x0_ugt_42:
+** cmp w0, 42
+** bls .L96
+** b taken
+** b not_taken
+*/
+
+/*
+** u32_x0_uge_42:
+** cmp w0, 41
+** bls .L98
+** b taken
+** b not_taken
+*/
+
+/*
+** i32_x0_slt_42:
+** cmp w0, 41
+** bgt .L100
+** b taken
+** b not_taken
+*/
+
+/*
+** i32_x0_sle_42:
+** cmp w0, 42
+** bgt .L102
+** b taken
+** b not_taken
+*/
+
+/*
+** i32_x0_sgt_42:
+** cmp w0, 42
+** ble .L104
+** b taken
+** b not_taken
+*/
+
+/*
+** i32_x0_sge_42:
+** cmp w0, 41
+** ble .L106
+** b taken
+** b not_taken
+*/
+
+/*
+** u64_x0_eq_42:
+** cmp x0, 42
+** beq .L109
+** b not_taken
+** b taken
+*/
+
+/*
+** u64_x0_ne_42:
+** cmp x0, 42
+** beq .L111
+** b taken
+** b not_taken
+*/
+
+/*
+** u64_x0_ult_42:
+** cmp x0, 41
+** bhi .L113
+** b taken
+** b not_taken
+*/
+
+/*
+** u64_x0_ule_42:
+** cmp x0, 42
+** bhi .L115
+** b taken
+** b not_taken
+*/
+
+/*
+** u64_x0_ugt_42:
+** cmp x0, 42
+** bls .L117
+** b taken
+** b not_taken
+*/
+
+/*
+** u64_x0_uge_42:
+** cmp x0, 41
+** bls .L119
+** b taken
+** b not_taken
+*/
+
+/*
+** i64_x0_slt_42:
+** cmp x0, 41
+** bgt .L121
+** b taken
+** b not_taken
+*/
+
+/*
+** i64_x0_sle_42:
+** cmp x0, 42
+** bgt .L123
+** b taken
+** b not_taken
+*/
+
+/*
+** i64_x0_sgt_42:
+** cmp x0, 42
+** ble .L125
+** b taken
+** b not_taken
+*/
+
+/*
+** i64_x0_sge_42:
+** cmp x0, 41
+** ble .L127
+** b taken
+** b not_taken
+*/
+
+/*
+** u8_x0_eq_42:
+** and w0, w0, 255
+** cmp w0, 42
+** beq .L130
+** b not_taken
+** b taken
+*/
+
+/*
+** u8_x0_ne_42:
+** and w0, w0, 255
+** cmp w0, 42
+** beq .L132
+** b taken
+** b not_taken
+*/
+
+/*
+** u8_x0_ult_42:
+** and w0, w0, 255
+** cmp w0, 41
+** bhi .L134
+** b taken
+** b not_taken
+*/
+
+/*
+** u8_x0_ule_42:
+** and w0, w0, 255
+** cmp w0, 42
+** bhi .L136
+** b taken
+** b not_taken
+*/
+
+/*
+** u8_x0_ugt_42:
+** and w0, w0, 255
+** cmp w0, 42
+** bls .L138
+** b taken
+** b not_taken
+*/
+
+/*
+** u8_x0_uge_42:
+** and w0, w0, 255
+** cmp w0, 41
+** bls .L140
+** b taken
+** b not_taken
+*/
+
+/*
+** i8_x0_slt_42:
+** sxtb w0, w0
+** cmp w0, 41
+** bgt .L142
+** b taken
+** b not_taken
+*/
+
+/*
+** i8_x0_sle_42:
+** sxtb w0, w0
+** cmp w0, 42
+** bgt .L144
+** b taken
+** b not_taken
+*/
+
+/*
+** i8_x0_sgt_42:
+** sxtb w0, w0
+** cmp w0, 42
+** ble .L146
+** b taken
+** b not_taken
+*/
+
+/*
+** i8_x0_sge_42:
+** sxtb w0, w0
+** cmp w0, 41
+** ble .L148
+** b taken
+** b not_taken
+*/
+
+/*
+** u16_x0_eq_42:
+** and w0, w0, 65535
+** cmp w0, 42
+** beq .L151
+** b not_taken
+** b taken
+*/
+
+/*
+** u16_x0_ne_42:
+** and w0, w0, 65535
+** cmp w0, 42
+** beq .L153
+** b taken
+** b not_taken
+*/
+
+/*
+** u16_x0_ult_42:
+** and w0, w0, 65535
+** cmp w0, 41
+** bhi .L155
+** b taken
+** b not_taken
+*/
+
+/*
+** u16_x0_ule_42:
+** and w0, w0, 65535
+** cmp w0, 42
+** bhi .L157
+** b taken
+** b not_taken
+*/
+
+/*
+** u16_x0_ugt_42:
+** and w0, w0, 65535
+** cmp w0, 42
+** bls .L159
+** b taken
+** b not_taken
+*/
+
+/*
+** u16_x0_uge_42:
+** and w0, w0, 65535
+** cmp w0, 41
+** bls .L161
+** b taken
+** b not_taken
+*/
+
+/*
+** i16_x0_slt_42:
+** sxth w0, w0
+** cmp w0, 41
+** bgt .L163
+** b taken
+** b not_taken
+*/
+
+/*
+** i16_x0_sle_42:
+** sxth w0, w0
+** cmp w0, 42
+** bgt .L165
+** b taken
+** b not_taken
+*/
+
+/*
+** i16_x0_sgt_42:
+** sxth w0, w0
+** cmp w0, 42
+** ble .L167
+** b taken
+** b not_taken
+*/
+
+/*
+** i16_x0_sge_42:
+** sxth w0, w0
+** cmp w0, 41
+** ble .L169
+** b taken
+** b not_taken
+*/
+
+/*
+** u8_x0_eq_65:
+** and w0, w0, 255
+** cmp w0, 65
+** beq .L172
+** b not_taken
+** b taken
+*/
+
+/*
+** u8_x0_ne_65:
+** and w0, w0, 255
+** cmp w0, 65
+** beq .L174
+** b taken
+** b not_taken
+*/
+
+/*
+** u8_x0_ult_65:
+** and w0, w0, 255
+** cmp w0, 64
+** bhi .L176
+** b taken
+** b not_taken
+*/
+
+/*
+** u8_x0_ule_65:
+** and w0, w0, 255
+** cmp w0, 65
+** bhi .L178
+** b taken
+** b not_taken
+*/
+
+/*
+** u8_x0_ugt_65:
+** and w0, w0, 255
+** cmp w0, 65
+** bls .L180
+** b taken
+** b not_taken
+*/
+
+/*
+** u8_x0_uge_65:
+** and w0, w0, 255
+** cmp w0, 64
+** bls .L182
+** b taken
+** b not_taken
+*/
+
+/*
+** i8_x0_slt_65:
+** sxtb w0, w0
+** cmp w0, 64
+** bgt .L184
+** b taken
+** b not_taken
+*/
+
+/*
+** i8_x0_sle_65:
+** sxtb w0, w0
+** cmp w0, 65
+** bgt .L186
+** b taken
+** b not_taken
+*/
+
+/*
+** i8_x0_sgt_65:
+** sxtb w0, w0
+** cmp w0, 65
+** ble .L188
+** b taken
+** b not_taken
+*/
+
+/*
+** i8_x0_sge_65:
+** sxtb w0, w0
+** cmp w0, 64
+** ble .L190
+** b taken
+** b not_taken
+*/
+
+/*
+** u16_x0_eq_65:
+** and w0, w0, 65535
+** cmp w0, 65
+** beq .L193
+** b not_taken
+** b taken
+*/
+
+/*
+** u16_x0_ne_65:
+** and w0, w0, 65535
+** cmp w0, 65
+** beq .L195
+** b taken
+** b not_taken
+*/
+
+/*
+** u16_x0_ult_65:
+** and w0, w0, 65535
+** cmp w0, 64
+** bhi .L197
+** b taken
+** b not_taken
+*/
+
+/*
+** u16_x0_ule_65:
+** and w0, w0, 65535
+** cmp w0, 65
+** bhi .L199
+** b taken
+** b not_taken
+*/
+
+/*
+** u16_x0_ugt_65:
+** and w0, w0, 65535
+** cmp w0, 65
+** bls .L201
+** b taken
+** b not_taken
+*/
+
+/*
+** u16_x0_uge_65:
+** and w0, w0, 65535
+** cmp w0, 64
+** bls .L203
+** b taken
+** b not_taken
+*/
+
+/*
+** i16_x0_slt_65:
+** sxth w0, w0
+** cmp w0, 64
+** bgt .L205
+** b taken
+** b not_taken
+*/
+
+/*
+** i16_x0_sle_65:
+** sxth w0, w0
+** cmp w0, 65
+** bgt .L207
+** b taken
+** b not_taken
+*/
+
+/*
+** i16_x0_sgt_65:
+** sxth w0, w0
+** cmp w0, 65
+** ble .L209
+** b taken
+** b not_taken
+*/
+
+/*
+** i16_x0_sge_65:
+** sxth w0, w0
+** cmp w0, 64
+** ble .L211
+** b taken
+** b not_taken
+*/
+
+/*
+** u32_x0_eq_65:
+** cmp w0, 65
+** beq .L214
+** b not_taken
+** b taken
+*/
+
+/*
+** u32_x0_ne_65:
+** cmp w0, 65
+** beq .L216
+** b taken
+** b not_taken
+*/
+
+/*
+** u32_x0_ult_65:
+** cmp w0, 64
+** bhi .L218
+** b taken
+** b not_taken
+*/
+
+/*
+** u32_x0_ule_65:
+** cmp w0, 65
+** bhi .L220
+** b taken
+** b not_taken
+*/
+
+/*
+** u32_x0_ugt_65:
+** cmp w0, 65
+** bls .L222
+** b taken
+** b not_taken
+*/
+
+/*
+** u32_x0_uge_65:
+** cmp w0, 64
+** bls .L224
+** b taken
+** b not_taken
+*/
+
+/*
+** i32_x0_slt_65:
+** cmp w0, 64
+** bgt .L226
+** b taken
+** b not_taken
+*/
+
+/*
+** i32_x0_sle_65:
+** cmp w0, 65
+** bgt .L228
+** b taken
+** b not_taken
+*/
+
+/*
+** i32_x0_sgt_65:
+** cmp w0, 65
+** ble .L230
+** b taken
+** b not_taken
+*/
+
+/*
+** i32_x0_sge_65:
+** cmp w0, 64
+** ble .L232
+** b taken
+** b not_taken
+*/
+
+/*
+** u64_x0_eq_65:
+** cmp x0, 65
+** beq .L235
+** b not_taken
+** b taken
+*/
+
+/*
+** u64_x0_ne_65:
+** cmp x0, 65
+** beq .L237
+** b taken
+** b not_taken
+*/
+
+/*
+** u64_x0_ult_65:
+** cmp x0, 64
+** bhi .L239
+** b taken
+** b not_taken
+*/
+
+/*
+** u64_x0_ule_65:
+** cmp x0, 65
+** bhi .L241
+** b taken
+** b not_taken
+*/
+
+/*
+** u64_x0_ugt_65:
+** cmp x0, 65
+** bls .L243
+** b taken
+** b not_taken
+*/
+
+/*
+** u64_x0_uge_65:
+** cmp x0, 64
+** bls .L245
+** b taken
+** b not_taken
+*/
+
+/*
+** i64_x0_slt_65:
+** cmp x0, 64
+** bgt .L247
+** b taken
+** b not_taken
+*/
+
+/*
+** i64_x0_sle_65:
+** cmp x0, 65
+** bgt .L249
+** b taken
+** b not_taken
+*/
+
+/*
+** i64_x0_sgt_65:
+** cmp x0, 65
+** ble .L251
+** b taken
+** b not_taken
+*/
+
+/*
+** i64_x0_sge_65:
+** cmp x0, 64
+** ble .L253
+** b taken
+** b not_taken
+*/
+
+/*
+** u8_x0_eq_0:
+** tst w0, 255
+** bne .L255
+** b taken
+** b not_taken
+*/
+
+/*
+** u8_x0_ne_0:
+** tst w0, 255
+** beq .L257
+** b taken
+** b not_taken
+*/
+
+/*
+** u8_x0_ult_0:
+** b not_taken
+*/
+
+/*
+** u8_x0_ule_0:
+** tst w0, 255
+** bne .L260
+** b taken
+** b not_taken
+*/
+
+/*
+** u8_x0_ugt_0:
+** tst w0, 255
+** beq .L262
+** b taken
+** b not_taken
+*/
+
+/*
+** u8_x0_uge_0:
+** b taken
+*/
+
+/*
+** i8_x0_slt_0:
+** tbnz w0, 7, .L266
+** b not_taken
+** b taken
+*/
+
+/*
+** i8_x0_sle_0:
+** sxtb w0, w0
+** cmp w0, 0
+** ble .L269
+** b not_taken
+** b taken
+*/
+
+/*
+** i8_x0_sgt_0:
+** sxtb w0, w0
+** cmp w0, 0
+** ble .L271
+** b taken
+** b not_taken
+*/
+
+/*
+** i8_x0_sge_0:
+** tbnz w0, 7, .L273
+** b taken
+** b not_taken
+*/
+
+/*
+** u16_x0_eq_0:
+** tst w0, 65535
+** bne .L275
+** b taken
+** b not_taken
+*/
+
+/*
+** u16_x0_ne_0:
+** tst w0, 65535
+** beq .L277
+** b taken
+** b not_taken
+*/
+
+/*
+** u16_x0_ult_0:
+** b not_taken
+*/
+
+/*
+** u16_x0_ule_0:
+** tst w0, 65535
+** bne .L280
+** b taken
+** b not_taken
+*/
+
+/*
+** u16_x0_ugt_0:
+** tst w0, 65535
+** beq .L282
+** b taken
+** b not_taken
+*/
+
+/*
+** u16_x0_uge_0:
+** b taken
+*/
+
+/*
+** i16_x0_slt_0:
+** tbnz w0, 15, .L286
+** b not_taken
+** b taken
+*/
+
+/*
+** i16_x0_sle_0:
+** sxth w0, w0
+** cmp w0, 0
+** ble .L289
+** b not_taken
+** b taken
+*/
+
+/*
+** i16_x0_sgt_0:
+** sxth w0, w0
+** cmp w0, 0
+** ble .L291
+** b taken
+** b not_taken
+*/
+
+/*
+** i16_x0_sge_0:
+** tbnz w0, 15, .L293
+** b taken
+** b not_taken
+*/
+
+/*
+** u32_x0_eq_0:
+** cbnz w0, .L295
+** b taken
+** b not_taken
+*/
+
+/*
+** u32_x0_ne_0:
+** cbz w0, .L297
+** b taken
+** b not_taken
+*/
+
+/*
+** u32_x0_ult_0:
+** b not_taken
+*/
+
+/*
+** u32_x0_ule_0:
+** cbnz w0, .L300
+** b taken
+** b not_taken
+*/
+
+/*
+** u32_x0_ugt_0:
+** cbz w0, .L302
+** b taken
+** b not_taken
+*/
+
+/*
+** u32_x0_uge_0:
+** b taken
+*/
+
+/*
+** i32_x0_slt_0:
+** tbnz w0, #31, .L306
+** b not_taken
+** b taken
+*/
+
+/*
+** i32_x0_sle_0:
+** cmp w0, 0
+** ble .L309
+** b not_taken
+** b taken
+*/
+
+/*
+** i32_x0_sgt_0:
+** cmp w0, 0
+** ble .L311
+** b taken
+** b not_taken
+*/
+
+/*
+** i32_x0_sge_0:
+** tbnz w0, #31, .L313
+** b taken
+** b not_taken
+*/
+
+/*
+** u64_x0_eq_0:
+** cbnz x0, .L315
+** b taken
+** b not_taken
+*/
+
+/*
+** u64_x0_ne_0:
+** cbz x0, .L317
+** b taken
+** b not_taken
+*/
+
+/*
+** u64_x0_ult_0:
+** b not_taken
+*/
+
+/*
+** u64_x0_ule_0:
+** cbnz x0, .L320
+** b taken
+** b not_taken
+*/
+
+/*
+** u64_x0_ugt_0:
+** cbz x0, .L322
+** b taken
+** b not_taken
+*/
+
+/*
+** u64_x0_uge_0:
+** b taken
+*/
+
+/*
+** i64_x0_slt_0:
+** tbnz x0, #63, .L326
+** b not_taken
+** b taken
+*/
+
+/*
+** i64_x0_sle_0:
+** cmp x0, 0
+** ble .L329
+** b not_taken
+** b taken
+*/
+
+/*
+** i64_x0_sgt_0:
+** cmp x0, 0
+** ble .L331
+** b taken
+** b not_taken
+*/
+
+/*
+** i64_x0_sge_0:
+** tbnz x0, #63, .L333
+** b taken
+** b not_taken
+*/
--
2.45.2

Re: [PATCH 7/8] AArch64: precommit test for CMPBR instructions

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