Richard Henderson wrote: > Tested only as far as cross-compile. I had a browse through > objdump of libatomic for a brief sanity check. > > Can you please test on real hw and report back?
I'll run a test, but a couple of things I noticed: > /* Shift the values to the correct bit positions. */ > - if (!(ac.aligned && MEM_P (cmp))) > - cmp = s390_expand_mask_and_shift (cmp, mode, ac.shift); > - if (!(ac.aligned && MEM_P (new_rtx))) > - new_rtx = s390_expand_mask_and_shift (new_rtx, mode, ac.shift); > + cmp = s390_expand_mask_and_shift (cmp, mode, ac.shift); > + new_rtx = s390_expand_mask_and_shift (new_rtx, mode, ac.shift); This seems to disable use of ICM / STCM to perform byte or aligned halfword access. Why is this necessary? Those operations are supposed to provide the required operand consistency ... > +(define_insn "atomic_loaddi_1" > + [(set (match_operand:DI 0 "register_operand" "=f,f") > + (unspec:DI [(match_operand:DI 1 "memory_operand" "R,m")] > + UNSPEC_MOVA))] > + "!TARGET_ZARCH" > + "@ > + ld %0,%1 > + ldy %0,%1" > + [(set_attr "op_type" "RX,RXY") > + (set_attr "type" "floaddf")]) This seems to force DImode accesses through floating-point registers, which is quite inefficient. Why not allow LM/STM? Those are supposed to provide doubleword consistency if the operand is sufficiently aligned ... [ From the Principles of Operations, section Block-Concurrent References: The instructions LOAD MULTIPLE (LM), LOAD MULTIPLE DISJOINT, LOAD MULTIPLE HIGH, STORE MULTIPLE (STM), and STORE MULTIPLE HIGH, when the operand or operands start on a word boundary; the instructions LOAD MULTIPLE (LMG) and STORE MULTIPLE (STMG), when the operand starts on a doubleword boundary; and the instructions COMPARE LOGICAL (CLC), COMPARE LOGICAL CHARACTERS UNDER MASK, INSERT CHARACTERS UNDER MASK, LOAD CONTROL (LCTLG), STORE CHARACTERS UNDER MASK, and STORE CONTROL (STCTG) access their storage operands in a left-to-right direction, and all bytes accessed within each doubleword appear to be accessed concurrently as observed by other CPUs. ] Otherwise the patch looks good to me. Thanks, Ulrich -- Dr. Ulrich Weigand GNU Toolchain for Linux on System z and Cell BE ulrich.weig...@de.ibm.com
